Search

This work presents the design of a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and a positive feedback bulk structure. The output stage comprises a simple circuit to reduce the total voltage overhead necessary to define the logic levels. The powering scheme of the pre-amplifier, with a floating reservoir capacitor, contributes to reduce the impacts of global process variability. The positive feedback bulk structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also provides positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in a 28 nm CMOS technology and reaches an IRN below of the quantization noise of a 10 bits differential ADCs working with 600 mV power supply. The dynamic comparator achieves 237 μV input-referred noise, while consuming only 38.8 fJ per comparison and having a nominal delay of 5.77 ns.

This paper presents a power-efficient Ultra Low Voltage (ULV) Fully-Differential (FD) Digital-Based Operational Transconductance Amplifier for Biomedical signal processing (BioDIGOTA), which digitally processes biological analog signals using CMOS standard-cells. Post-layout simulations, including parasitic effects in 180nm CMOS technology, show that BioDIG- OTA consumes only 144 nW at 300 mV of supply voltage while driving a 20 pF capacitive load, with a power efficiency factor (PEF) lower than 1. The layout occupies 0.03 mm2 total silicon area, excluding I/0 pads. The proposed BioDIGOTA proves that digital-based analog design can be adopted in biomedical signal amplifiers, lowering the total silicon area by 2.3X times compared to the current state of the art landscape while keeping reasonable power and system performance.

An ultra-low voltage and ultra-low power Digital-Based Operational Transconductance Amplifier (DB-OTA) is presented and demonstrated on silicon in 180 nm CMOS. The DB-OTA is designed using digital standard cells, hence benefitting from technology scaling as much as digital circuits, while also being technology- and design-portable, and requiring minimal design and integration effort compared to conventional analog-intensive OTAs. The fabricated DB-OTA testchip occupies a compact area of 1,426 $\mu \text{m}^{2}$ , operates at supply voltages down to 300 mV, and consumes only 590 pW while driving a capacitive load of 80pF. Its measured Total Harmonic Distortion (THD) is lower than 5% at a 100-mV input signal swing. Based on these results, the proposed DB-OTA achieves 2,101 V−1 small-signal figure of merit (FOMS) and 1,070 large-signal figure of merit (FOML). To the best of the authors’ knowledge, the power is the lowest reported to date in an OTA, and the achieved figures of merit are the best in sub-500 mV OTAs reported to date. The low cost, the low design effort and the high power efficiency of DB-OTA make it well suited for purely harvested low-frequency analog interfaces in sensor nodes.

This work presents the analysis, design, and performance evaluation of three usual CMOS proportional to absolute temperature (PTAT) voltage generators, with emphasis on variability effects. Minimization or compensation of the main error sources, such as fabrication variability and intrinsic non-linearities, is an important design challenge required to increase the precision and robustness of a voltage reference. The CMOS PTAT topologies are analytically described and design methodologies for PTAT circuits in subthreshold are presented. The compromises between design conditions and resulting performance are evaluated through simulation for these three PTAT generators, including linearity with temperature, temperature coefficient (TC), and variability impact. Monte-Carlo simulations demonstrated the sensitivity of each topology to fabrication variability, showing that the self-cascode MOSFET structure presents the best accuracy of TC, nominal PTAT voltage, and linearity with temperature.

This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from −40 to 125 °C, a power supply rejection ratio (PSRR) of −54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm2.

This paper presents a fully-integrated 32.7 kHz relaxation oscillator designed in TSMC 40 nm CMOS for IoT applications. Simulation results show that the proposed relaxation oscillator consumes 40 nW at room temperature from 0.6 V power supply. The architecture achieves a temperature coefficient (TC) as low as 12.5 ppm/°C (μ = 35.5 ppm/°C for 400 samples) from −40°C to 125°C. Also, more than 50% of samples have a TC less than 30 ppm/°C. The oscillator also has a fast start-up time, achieving a steady-state of the operating frequency within 3 cycles. The energy efficiency is 1.22 nW/kHz, and the entire circuit occupies an active area of 0.127 mm2.

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

This paper proposes a wideband 0.4-2 GHz cascode common-gate LNA that can be used as a building block for a noise canceling topology (which entails its noise to be canceled at the output node). The design strategy is to set the operating point by analyzing the third order coefficient $(\alpha_{3})$ of the output current and the output voltage, which is designed using a load composed by a diode-connected PMOS transistor and a resistor in parallel. This operating point allows a reasonable $V_{GS}$ spread, maintaining a high IIP3 which implies a low IIP3 sensitivity to process variability. The design strategy also achieves a current consumption under 1 mA and, depending on the technology node $V_{DD}$ (CMOS 130 nm in this case), it can consume under 1 mW of power. This makes the wideband LNA suitable for IoT applications. Monte Carlo simulations have been carried out to demonstrate the operating region sensitivity to variability and achieves a result of worst case $IIP3_{\mu}=+0.2\ \mathrm{dBm}$ with $\sigma=0.8\ \mathrm{dBm}$ (@2GHz) up to a nominal 2.75 dBm @900 MHz, $S_{11} (canceled by virtue of its topology), a voltage gain of 11.6-14.6 dB ( $S_{21}=6.4-9.4\ \mathrm{dB}$ with a buffer to $50\ \Omega$ ), and consuming just 1.19 mW from a 1.2 V supply.

This work presents the design of a narrowband Low Noise Amplifier (LNA) that is a part of a transponder project of a UHF satellite for the Brazilian Environmental Data Collecting System (SBCDA). The proposed LNA operates at 401.635 MHz moreover, it provides 28dB of power gain, 3.6dB of noise figure (NF), IIP3 of -28 dBm and 6.53 mW of power consumption and it was designed in a standard 130 nm CMOS process.

This paper presents a power-efficient Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifier (DB-OTA), which uses static logic gates and processes digitally the analog input signal. Post-layout simulations in 180nm CMOS technology show that at 300mV supply voltage the circuit consumes just 2nW while driving a capacitive load of 80pF with Total Harmonic Distortion lower than 5% at 100mV input signal swing. The total silicon area is $1,426\ \mu \mathrm{m}^{2}$ . The maximum energy efficiency supply for the DB-OTA and its scalability to 40nm CMOS technology node are also demonstrated.

A voltage reference based on MOSFETs operated under Zero Temperature Coefficient (ZTC) bias is proposed. The circuit operates in a power supply voltage range from 0.3 V up to 1.2 V and outputs three different reference voltages using Standard- $V_{T}$ (SVT), Low- $V_{T}$ (LVT), and Zero- $V_{T}$ (ZVT) MOS transistors biased near their ZTC point by a single PTAT current reference. Measurements on 15 circuit samples fabricated in a standard 0.13- $\mu \text{m}$ CMOS process show a worst-case normalized standard deviation $(\sigma /\mu)$ of 3% (SVT), 5.1% (LVT) and 10.8% (ZVT) respectively with a 75% of confidence level. At the nominal supply voltage of 0.45 V, the measured effective temperature coefficients (TCeff) range from 140 to 200 ppm/°C over the full commercial temperature range. At room temperature (25 °C), line sensitivity in the ZVT VR is just 1.3%/100 mV, over the whole supply range. The proposed reference draws around 5 $\mu \text{W}$ and occupies 0.014 mm2 of silicon area.

In this work a resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere consumption range, and under 1 V of power supply. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results are presented for two CMOS processes, XFAB 0.18 μm and IBM 0.13 μm. Experimental results from one fabrication run demonstrate a reference voltage of 570 mV, with a temperature coefficient as low as 11 ppm/°C for the 0---125 °C range, while the power consumption of the whole circuit is 5 nW under a 0.9 V supply at 27 °C. The occupied silicon area is 0.0022 mm$$^2$$2.

This work presents a six phase Switched Capacitor (SC) DC — DC converter for photovoltaic Energy Harvesting designed in a 130 nm CMOS process for commercial motes application and Internet of Things (IoT). It tracks the Maximum Power Point (MPP) of a commercial 3 cm × 3 cm 60 mW poly-crystalline photoelectric panel through switching frequency modulation aiming battery recharge. Open-circuit voltage ratio was the chosen Maximum Power Point Tracking (MPPT) strategy. The converter achieves a maximum power conversion efficiency of 90 % for input power higher than 30 mW and is designed to operate with input voltages from 1.25 V to 1.8 V, resulting output voltages from 2.5 V to 3.6 V, respectively. Peripheral circuitry also includes an output over-voltage protection of 3.6 V and the control circuits, that consumes a total of 850 μA at 3.3 V. Complete layout consumes 300 × 700 μm2 of silicon area. The only external components are 6×100 nF capacitors.

The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology proposed here is based on the resistive-feedback inverter with a cascaded auxiliary amplifier to implement noise canceling. This cascaded amplifier is composed by a common-source (CS) amplifier and a very linear buffer at the output of the cascade. The high IP2 is obtained by a proper transistor biasing and by combining diodes with the load of the amplifiers with the highest non-linearity. This topology also works as a balun to comply with single-ended input from antennas and differential mixers as output loads. The post-layout simulations included bondwire inductances and pad capacitances parasitics. The results show a bandwidth of 50 MHz–1 GHz, voltage gain > 18 dB, NF < 3.8 dB, Sn < −13 dB and maximum IP2 of 38 dBm. The LNA power consumption is just 6.7 mW, excluding pad buffers.

Complementary Metal Oxide Semiconductor (CMOS) Transconductors, or Gm cells, are key building blocks to implement a large variety of analog circuits such as adjustable filters, multipliers, controlled oscillators and amplifiers. Usually temperature stability is a must in such applications, and herein we define all required conditions to design low thermal sensitivity Gm cells by biasing MOSFETs at Transconductance Zero Temperature Condition (GZTC). This special bias condition is analyzed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are designed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits have been simulated in a 130 nm CMOS commercial process, resulting in improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/oC.

This work presents a high PSRR nano-watt resistorless thresh old voltage (VTo) monitor circuit that can be used in temperature sensors, voltage and current references, radiation dosimeters and other applications such as fabrication process monitoring and verification. In this circuit design the MOS transistors operate in subthreshold and near-threshold regimes, the circuit analysis is based on a current-voltage relationship derived from a continuous physical MOSFET model, valid from weak to strong inversion. The bias condition is established from the equilibrium between two self-cascode cells operating at different inversion levels, and the high PSRR results from a high gain feedback path. The circuit is MOSFET-only, and can be implemented in any standard digital CMOS process. Post-layout simulations show that it operates with less than 1 V of power supply, consuming only tens of nW, and resulting in a VT0 error lower than 1%, when compared to its modeling value, for a −40 to +125°C temperature range. A very high rejection to VDD variation is achieved in this design, with PSRR lower than −63.9 dB at 100 Hz, and a line sensitivity lower than 252 ppm/V was found for a supply range from 1 V to 3 V. Monte-Carlo simulations are presented to evaluate the fabrication variability sensitivity, presenting a maximum error of 4% for a 3a spread range. The circuit area is very small, around 0.0047 mm2 including the start-up stage.

Digital and analog ICs generally rely on the concept of matched behavior between identically designed devices. Time-independent variations between identically designed transistors, called mismatch, affect the performance of most analog and even digital MOS circuits. This article focuses on the analysis of mismatch in MOS transistors resulting from random fluctuations of the dopant concentration, first studied by Keyes. Today, we recognize these fluctuations as the main cause of mismatch in bulk CMOS transistors.

This work presents a study of the CMOS based R-2R ladder network (also called M-2M) Digital-to-Analog Converter (DAC) as a potential candidate for ultra-low voltage (ULV) applications, i.e. supply voltages VDD lower than 200mV. MOS transistors operate in subthreshold under such very low VDD, and the circuit analysis must be done using an all-region continuous MOSFET model. Simulation results in a commercial 130 nm process corroborate the presented analysis, showing that it is possible to implement this DAC topology for 6 to 8 bits operating under supply voltages from 70 mV to 140 mV.

The continuous scaling of CMOS devices has required the consequent reduction of the supply voltages. There is a need for analog and RF circuits able to operate under at supplies lower than 0.5 V. This paper presents a voltage reference based on the MOSFET zero-temperature condition (ZTC) that operates with a low 0.5 V supply. The circuit is composed by a diode-connected MOS transistor operating near the ZTC condition that is biased by a proportional-to-absolute-temperature (PTAT) current reference implemented with Schottky-diodes. The ZTC condition is analysed using a continuous MOSFET model that is valid from weak to strong inversion and the circuit behaviour is described by theoretical expressions. Our reference circuit is designed for 3 versions: each with MOSFETs of different threshold voltage (standard-VT, low-VT, and zero-VT), all available in the 130 nm CMOS process used. These designs result in three different and very low reference voltages: 312, 237, and 51 mV. All 3 designed reference operate in the range of 0.45 to 1.2 V of supply voltages, consuming 1 uA of typical supply current. Post-layout simulations present a Temperature Coefficients (TCs) of 214, 372, and 953 ppm/°C in a temperature range from -55 to 125°C, respectively. Monte-Carlo simulations show the fabrication variability impact on the circuit performance. The voltage reference was designed in a 130 nm process and it uses 0.014 mm2 of silicon area.

The necessary conditions to design MOSFET transconductors with low temperature dependence are analysed and defined in this paper. Transconductors, or Gm circuits, are fundamental blocks used to implement adjustable filters, multipliers, controlled oscillators, amplifiers and a large variety of analog circuits. Temperature stability is a must in such applications, and herein we show a strategy that can be used to improve the temperature stability of these transconductors by biasing MOSFETs at transconductance zero-temperature condition (GZTC). This special bias condition is analysed using a MOSFET model which is continuous from weak to strong inversion, and it is proved that this condition always occurs from moderate to strong inversion operation in any CMOS fabrication process. Additionally, a few example circuits are proposed using this technique: a single-ended resistor emulator, an impedance inverter, a first order and a second order filter. These circuits were simulated in a 130 nm CMOS commercial process, resulting improved thermal stability in the main performance parameters, in the range from 27 to 53 ppm/°C.

In this work a novel resistorless sub-bandgap voltage reference (BGR) is introduced. It is a self-biased and small area topology that works in the nano-ampere current consumption range, and under 1 V of power supply. The analytical behavior of the circuit is described, and simulation results for a standard 0.18 μm CMOS process are analysed. A reference voltage of 479 mV is demonstrated, with a temperature coefficient of 8.79 ppm/oC for the 0 to 125 °C range, while the power consumption of the whole circuit is 4.86 nW under a 0.9 V power supply at 27 oC. The estimated silicon area is 0.0012 mm2.

A self-biased current reference based on the MOSFET Zero Temperature Coefficient (ZTC) condition is presented. It can be implemented in any CMOS process and it provides a simple alternative to design a reference current suitable for low TC biasing. This topology was designed in a 0.18 μm process to generate 5 μA under a supply voltage from 1.4V to 1.8 V, spending a silicon area around 0.010mm2. From circuit simulations, the current reference is estimated to have a temperature coefficient (TCeff) of 15 ppm/°C from -40 to +85 °C and a fabrication sensitivity of σ/μ = 4.5%, including average process and local mismatch variability. The power supply sensitivity resulted around 1%V for this new reference.

This work presents a novel Switched-capacitor Bandgap Voltage Reference (SCBGR) circuit that dispenses entirely the use of resistors. The vEB negative drift and the thermal voltage (VT) positive drift voltages are both generated by the same PNP vertical bipolar transistor, avoiding diode mismatch problems. The current sources that are used to generate different junction current densities are averaged in the switching process, reducing their mismatch impact on the circuit performance. A switched-capacitor circuit stores and processes these voltages, generating the bandgap reference voltage after 5 clock cycles. Since capacitors are used instead of resistors, variability problems like average process spread and device mismatches are reduced. The proposed topology was designed and simulated in CMOS for 180 nm process. This paper presents a systematic comparison to the traditional dual-BJT BGR and demonstrates the better performance of this new topology with respect to the former. Monte Carlo simulation shows significantly lower spread resulting from variations in the output reference voltage and in its temperature coefficient (TC).

A novel resistorless bipolar junction transistor (BJT) bias and curvature compensation circuit for ultra-low-power CMOS bandgap voltage references (BGRs) is introduced. It works in the nanoampere current consumption range and under 1 V of power supply. The analytical behaviour of the circuit is described and simulation results for a 0.18 μm CMOS standard process are analysed. A junction voltage of 550 mV at room temperature is obtained (at an emitter current of 3.5 nA), presenting an almost linear temperature dependence, whereas the power consumption of the whole circuit is 3.4 nW under a 0.8 V power supply at 27°C. The estimated silicon area is 0.00135 mm 2 .

This paper presents a new approach for accurate M-2M MOSFET digital-to-analog converter (DAC) design. It describes a complete design methodology, where DAC inaccuracy is related to transistor geometry and bias through a powerful physics-based MOSFET mismatch model, very useful for hand design. Short-channel effects are also taken into account. Two versions of the converter were implemented in a 0.35 mum 3.3 V CMOS technology, and corroborate the theoretical development with statistical experimental results.

Component tolerances and mismatches due to process variations severely degrade the performance of bandgap reference (BGR) circuits. In this paper, the authors describe the design of a BGR considering the Pelgrom's mismatch model. The main purpose of our methodology is to convey the design to reach a good trade-off between area and mismatch. Implemented in standard 0.35mum CMOS technology, the circuit also includes a straightforward 4-bits trimming circuit to achieve more process variations independence. Its Monte Carlo temperature coefficient average is 40-ppm/degC and the reference output voltage average is 1.230V. The area of the BGR is 400x350mum2 due to our design matching requirements.

Errors caused by tolerance variations and mismatches among components severely degrade the performance of integrated circuits. These random effects in process parameters significantly impact manufacture costs by decreasing yield and so by including extra-circuits for adjustment. In this paper we propose a design methodology based on the Pelgrom's MOS transistor-mismatching model devices. Our main objective is to calculate the size of each component considering their relation between area and mismatching. Therefore, in order to validate our proposal methodology, we used as a design target a bandgap reference circuit fabricated in 0.35 mum CMOS technology. Its temperature coefficient attains an average value of 40ppm/degC and an average output voltage of 1,20714V. It also includes a straightforward 4-bits trim circuit to achieve more process independence variation. As a result of our methodology, the considerable area of 400 times 350 mum2 was occupied due to our matching design requirements

This paper presents a compact model for MOS transistor mismatch. The mismatch model uses the carrier number fluctuation theory to account for the effects of local doping fluctuations along with an accurate and compact dc MOSFET model. The resulting matching model is valid for any operation condition, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters. Experimental results from a set of transistors integrated on a 0.35 /spl mu/m technology confirm the accuracy of our mismatch model under various bias conditions.

Electron device matching has been a key factor on the performance of today's analog or even digital electronic circuits. This paper presents a study of drain current matching in MOS transistors. CMOS test structures were designed and fabricated as a way to develop an extensive experimental work, where current mismatch was measured under a wide range of bias conditions. A model for MOS transistor mismatch was also developed, using the carrier number fluctuation theory to account for the effects of local doping fluctuations. This model shows a good fitting with measurements over a wide range of operation conditions, from weak to strong inversion, from the linear to the saturation region, and allows the assessment of mismatch from process and geometric parameters.

Postprint This work presents an approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 /spl mu/m CMOS technology corroborate the theoretical development of this work.