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This study presents a design of a 94-GHz high-performance and highly compact frequency-modulated continuous-wave radar sensor. In this sensor, an X-band CMOS-based all-digital phase-locked loop chip, W-band SiGe-based transceiver monolithic microwave integrated circuit (MMIC), and W-band GaN-based MMIC power amplifier (PA) are heterogeneously integrated (HI). Each part of the 130-nm bipolar complementary metal-oxide-semiconductor (BiCMOS) SiGe-based transceiver MMIC is designed to include a low-noise amplifier, PA, octupler, mixer, and lange coupler. The fabrication process of our in-house silicon-based MEMS photosensitive composite film is developed to provide very high-density integration and very low insertion loss of interconnections between chips. The HI front end of the radar sensor is measured on-wafer with a high output power of 22 dBm. Moreover, a low double-sideband noise figure (NF) of 10.2 dB is obtained. Bonding-substrate integrated waveguide (SIW)-WG transitions between the heterogeneously integrated front end and the antenna are specially designed and verified. A 2.3-dB degradation is observed, where 19.7 dBm is measured at the transmitter WG WR-10-flange. Thus, the sensor offers a 55-dB dynamic range at a 2-m position with an expectation of a long-distance target-detection range. The radar sensor has an 11.7-cm range resolution and is only 60 x 40 x 8 mm³ in size, with a weight of only 78 g.

This letter presents a millimeter-wave silicon-germanium (SiGe) distributed attenuator which uses a transformer-based attenuation core. The nonlinearities of the SiGe heterojunction bipolar transistor (HBT) are managed using an RC-load, which linearizes the device impedance versus bias. In addition, a dual-resonance transformer is used to support broadband operation, while providing control over the attenuator insertion phase. Two attenuators, one using transmission line-based impedance transformers, and one using transformer-based impedance transformers, were designed and fabricated in a 180-nm SiGe bipolar and CMOS (BiCMOS) technology platform. The attenuators achieve competitive performance in terms of bandwidth and phase error, but with low insertion loss and large attenuation range.

Recently emerging applications in the millimeter-wave (mm-wave) frequency range, such as automotive radar, satellite communications, 5G, 6G, and beyond, have brought new and significant challenges to the implementation of microwave circuits and systems. Many of these, such as speed, power consumption, signal-handling capability, linearity, integration possibilities, and cost, are directly related to the choice of the semiconductor process technology. For the implementation of a sophisticated mm-wave front end, different technology options are available, mainly the group III–V semiconductors, silicon–germanium (SiGe) heterojunction bipolar transistor/bipolar CMOS (BiCMOS), or CMOS processes in their multiple variants [1] – [3] .

A high-efficiency 27–30 GHz 0.13- ${{\mu } \text {m}}$ BiCMOS transmitter front end for mobile satellite communication (SATCOM) phased arrays is presented. A system-level analysis for determining the key parameters of the RF front end for the case of a SATCOM user terminal for geostationary Earth orbit (GEO) is presented. The building blocks of the beamformer, consisting of a phase shifter, variable attenuator, and power amplifier, are fully characterized. A 360° phase shifter with an accuracy of 7 bits and amplitude error of ±1.5 dB is integrated with a variable attenuator that provides a gain variation of 16 dB with phase error of ±5°. The chip has a measured transducer gain of 23 dB and a power consumption of 45 mW at OP1dB of 10.8 dBm. The power-added efficiency (PAE) of 26.7% is measured for the entire channel at OP1dB. An error vector magnitude (EVM) of −28 dB at Pout,avg of 6 dBm and PAEavg of 12% is measured for a 400-MHz bandwidth 64-QAM modulated signal. The overall size of the chip is ${1.18} \times {2.23}\,\,\text {mm}^{{2}}$ .

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35 $\mu {\mathrm{ m}}$ SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration in the fuse link. A T0 analysis of CoSi shows link resistance scaling and temperature characteristics. Discrete eFuses were also subjected to 100ns Transmission Line Pulse (TLP) to compare ESD handling and robustness, and the associated MOSFET circuitry characterized for safe operating area (SOA) under DC and pulsed conditions. The analysis was expanded to look at the difference between the blow FET DC (reflected in the device models) and the pulsed FET (TLP) behavior (not captured in Design Kits). This work demonstrates the compatibility of electrically programmable fuse (eFuse) technology across a range of process technology nodes, as well as its robustness in high reliability applications.

This letter presents a 210–291-GHz $8\times $ multiplier chain in the 0.13- $\mu \text{m}$ SiGe Bipolar CMOS (BiCMOS) technology for the broadband generation of carrier signals, imaging, and spectroscopy. It consists of three cascaded Gilbert-cell doublers with compact input matching networks to generate quadrature collector currents in the switching quad for broadband flat conversion gain. The multiplier chain generates a saturated output power of −7.7 dBm at 244.5 GHz with a 3-dB bandwidth of 81 GHz. It consumes 0.24 W of dc power and occupies 0.86 mm 2 of chip area.

This letter shows a fully differential linear transimpedance amplifier designed for the emerging coherent optical communications for high data rate transmissions. The purpose of this letter is to present a possible solution in 28-nm CMOS technology instead of the most frequently used BiCMOS. The idea is to take advantage of the linearity of CMOS to partially offset its inherently lower transconductance over current ratio, which typically limits the bandwidth. The proposed TIA presents a −3-dB bandwidth equal to 42 GHz and its transimpedance gain can be programmable from 78 to 36 dB $\Omega $ with four variable gain stages. At maximum gain, the measured average input noise is equal to 18 pA/√Hz whereas the maximum total harmonic distortion for an output voltage swing of 500-mV peak-to-peak differential is always lower than 1.8% over the entire gain range. The complete transimpedance amplifier including the bias and dc offset cancellation circuits consumes 319 mW from a 2.4-V supply voltage.

The schematic of class-AB yield stage with BJT, CMOS, BiCMOS is carried out in cadence virtuoso simulator. Every transistor size in the operational amp is designed, validated and BiCMOS operated at supply voltage of 3.3V. The proposed amplifier circuit utilizes a class-AB output stage comprising of PMOS and NMOS transistors along with NPN an PNP push pull circuit is made use. The BiCMOS circuit is made use to achieve advantage of CMOS as well as bipolar. Then, at that point Cascode amplifier stage-based op amp using CMOS Class-AB output and Cascode amplifier stage-based op amp using BiCMOS Class-AB output are compared.

This paper presents a 27.0-30.5 GHz sub-sampling PLL implemented in a 0.18um SiGe BiCMOS process. The PLL incorporates an improved Class-C VCO with a supply-side 2nd-harmonic common-mode resonance and a completely floating, transformer-based 3rd-harmonic differential-mode resonance. Despite the limitation of the 0.18µm CMOS devices at high frequencies, the prototype achieves record low in-band noise of - 116dBc/Hz at 100kHz offset and sub-50fs RMS jitter at 30GHz when integrated from 1kHz to 100MHz, outperforming state-of-the-art designs in advanced CMOS nodes with similar output frequencies. A single low voltage of 1.8V is used for both CMOS-and SiGe-based blocks. At 40mA, the PLL achieves an excellent jitter FoM of -247.8dB when the FLL is turned on and -250.4dB when turned off.

A current-mode photon-counting circuit is proposed for long-range LiDAR applications to interface with a microchannel plate (MCP) photomultiplier tube (PMT). Based on the idea of a current-mode comparator, the proposed topology combines a BiCMOS regulated cascode current buffer together with a CMOS current comparator. The circuit accepts two input current signals, the photodetector current and a user-adjustable threshold current, and outputs a 1.8-V digital signal depending on the polarity of the difference current. Designed and characterized in a 180-nm SiGe BiCMOS process, the proposed design provides a 50-Ω input impedance up to 2-GHz and can detect 8-uA current pulses with widths of 300-ps FWHM at a count rate of 1-GHz. The solution also offers a low static power consumption of 4.07mW/channel dissipated from a 2.5-V and 1.8-V dual supply.

Semiconductor companies are developing ever faster interfaces to satisfy the need for higher data throughputs. However, the parasitic capacitance of the traditional ESD solutions limits the signal frequency. This paper demonstrates low-cap Analog I/Os for high speed SerDes (28Gbps to 112Gbps) circuits created in advanced BiCMOS, SOI and FinFET nodes.

This paper presents a 128 Gb/s single-ended linear trans-impedance amplifier (TIA) intended for use in receivers for 400G Ethernet optical modules and co-packaged optics. The inverter-based shunt-feedback TIA is implemented in a 22 nm FinFET CMOS process. It supports a record data rate of 128 Gb/s PAM4 and provides a DC trans-impedance gain of $59.3\ \text{dB}.\Omega$ while dissipating only 11.2 mW of power from a 0.8 V supply. Series and shunt inductive peaking techniques are used to achieve a 3-dB trans-impedance bandwidth of 46 GHz with a competitive input referred noise density of $12.6\ \text{pA}/\sqrt{\text{Hz}}$ . These results improve upon state-of-the-art BiCMOS/CMOS linear TIAs, demonstrating the potential for highly integrated, low-cost, high-sensitivity 100+G CMOS optical receivers in this process technology.

With the advances of thin-film process technology in foundry services, recent development is to design thermoelectric generator (TEG) with in-plane thermocouple of polysilicon or polycrystalline silicon germanium by complementary metal oxide semiconductor (CMOS) or BiCMOS process. However, the small thermal resistance and adversely large electrical resistance in a thermocouple of micron dimension lead to small temperature gradient and excessive heat loss, hence resulting in poor harvester performance. The optimal design of thermocouple dimension is therefore critical to the TEG performance. A model of the effect of thermocouple dimension on the TEG performance is developed. For the TEG design by TSMC CMOS process with P- and N-thermoleg of thickness $0.275~\mu \text{m}$ and $0.180~\mu \text{m}$ , respectively, the model shows that the optimal thermocouple is $60\,\,\mu \text {m} \times 2\,\,\mu \text{m}$ (length $\times $ width). For design by TSMC BiCMOS process with P- and N-thermoleg of thickness $0.380~\mu \text{m}$ and $0.200~\mu \text{m}$ , respectively, it is $45\,\,\mu \text {m} \times 2\,\,\mu \text{m}$ . The numerical simulation and experimental verification on the latter show that better TEG performance can be achieved by optimal thermocouple dimension to match the electrical and thermal resistances.

An analysis of timing and input-referred offset of sense amplifiers (SA) is presented, and a new SA architecture with capacitive offset correction is proposed. Offset sources are first analyzed in a cross-coupled latch-based SA design, and the analysis is then extended to the proposed SA. The results show the proposed offset correction technique can reduce the total sensing time by up to 40%, while eliminating dynamic offset due to the difference in resolving inverters trip points. A self-timed SRAM with a new replica timing structure is designed to generate optimal SA enable timing with respect to the total input-referred offset. Calculations for timing delay and offset are compared with simulation results in both a conventional and a proposed SA design. The presented simulation results are based on a 10 Kb CMOS SRAM array in 130 nm BiCMOS SiGe technology operating at a 500 MHz clock and 1.5 V supply.

Many RFID Components are either discrete components or integrated circuits components. With high demand and huge RFID market in supply and chain management, more RFID systems will employ integrated circuit components. This is due to cost competitiveness in using integrated circuit components. Understanding of these advanced components is therefore essential for the development of advanced RFID system. This chapter emphasizes on the practical design of advanced RFID components namely the tag and the reader. This chapter discusses the design methodology of integrated circuit. The technology such as Silicon Bipolar and Silicon CMOS are studied in this chapter; the focus is on understanding the advantages and disadvantages of using these technologies for the design of advanced RFID components. The architecture or circuit topology of reader and tag are also thoroughly discussed; the integration of features which normally reduces the number of discrete components is the focus of this topic. The circuit technique in designing the tag and reader is studied and analyzed. The current research trend in RFID integrated circuit is more on reader than tag. SiGe BiCMOS (Chiu et al., 2007), 0.18 μm CMOS (Wang et al., 2007, Khannur et al., 2008) are amoung technologies used in the latest reader resarch and product. The measurement methodology of advanced RFID components is also discussed in the last topic. Overall this chapter provides basic knowledge to the readers for further research in RFID integrated circuits. The understanding in advances of RFID components design, namely the technology, design techniques and test enables one to pursue in effective design of the state of the art RFID systems.

Radiation-oriented (RO-) and microwave (MW) characterization of the several process technologies – CMOS silicon-on-insulator (SOI) 180 nm process, CMOS 90 nm process, SiGe BiCMOS 0.42/0.25 µm process, GaAs heterojunction bipolar transistor (HBT) 2 µm process and GaAs pseudomorphic high electron mobility transistor (PHEMT) 0.5 µm process, which suitable for the development of radiation-tolerance transceiver integrated circuits with operating frequencies up to 30 GHz are presented. The results of MW-characterization showed two process technologies manufacturing in "foundry" mode – CMOS SOI 180 nm and CMOS 90 nm potentiality for the development of transceiver ICs with operating frequencies above 3 GHz and 12 GHz respectively. Obtained experimental results allow to determine radiation-tolerance indicators for the total ionizing dose, neutrons, impulse exposure and heavy ions and specify critical elements and IP-block fragments for given processes. Experimental data can be used at the first step of reasonable choice of process technologies for radiation-tolerant transceiver design.

Several 400G Ethernet standards (e.g. 400G-DR4/FR4) have been developed to address the rapid increase in interconnect BW demand created by data-centric computing [1]. Low-cost100Gb/s PAM-4 optical transceivers are critical to spur their adoption in high volume by data centers. While low-cost integrated silicon-photonic 100Gb/s PAM-4 transmitters have been demonstrated recently, the electronics in current receiver solutions is more disaggregated. They typically employ a standalone BiCMOS TIA 1C followed by a 100G PAM-4 (ADC+DSP)-based SerDes 1C (designed to equalize high-loss electrical channels), which results in higher power dissipation and package cost. To address these drawbacks, we present a 100Gb/s PAM-4 optical RX with a single-chip Solution integrating all 0f the RX electronics in a bulk CMOS process. While standalone l00Gb/s PAM-4 CMOS linear TIAs have been shown in prior work [2], [3], their integration with subsequent SerDes has not yet been demonstrated.

The paper presents constructing sub-THz frequency range transceiver’s basic principles. The opportunity of implementing a terahertz short-range automotive locator MMIC receiver is demonstrated. The article discusses possible terahertz range device applications. The prototype receiver's research results are presented. SiGe technology-based RF mixer and oscillator model for the future receiving and transmitting path devices implementation are presented.

An analogue intensive implementation of the baseband signal processing for a short range FMCW radar is presented. The intended use of the radar is proximity sensing. The choice for an analogue implementation is driven by the expected low production volume. This rules out small-feature size CMOS processes due to the start-up cost. The lower production volume combined with integration with the RF front-end leads to a BiCMOS implementation. The CMOS part uses a less advanced technology which in turn favours the use of an analogue intensive implementation of the baseband processing instead of a digital intensive implementation. This combination allows to pursue single chip integration with the RF front-end. The single chip allows to reduce the volume of the complete radar solution.

To elaborate the use of an electromagnetic spectrum in the terahertz range for several emerging applications such communication, computing, imaging, and sensing, the design of highly efficient, compact, and reliable integrated circuits is an indispensable requirement which has several potential challenges. The need of compact, efficient, high-performance sensing devices, which are operable at low power and deployable at a large scale, must play a significant role for integrated circuit technology. The concept and design of terahertz integrated circuit (THz-IC) technology for imaging and sensing applications is presented in this chapter. This chapter begins with silicon-based THz-IC technology and is followed by antenna arrays for imaging and sensing applications. The integrated circuit technology of choices such as electronics, photonics, or electronics-photonics hybrids depends on the application, which can be particularly diverse, spanning from sensing, spectroscopy, and imaging to wireless communication. As the antenna size shrinks quadratically as the radiation frequency increases for a given gain, the on-chip antennas have great potential in the terahertz range by eliminating packaging issues for cost-effective, compact terahertz transceivers. To achieve significantly high radiation efficiency, the loss mechanisms of several on-chip antenna technologies are presented, which is a challenging task.

International audience; This article presents an innovative architecture for the implementation of an electrostatic discharge (ESD) protection for millimeter-wave (mm-wave) devices. The proposed architecture is based on the use of 3-dB couplers, whose coupled outputs have been shorted to the ground node. In order to reduce the physical dimensions of the 3-dB coupler and to reach the high coupling required for this application, the Coupled Slow wave CoPlanar Waveguides (CS-CPWs) architecture was favored. The demonstrator of the proposed system was fabricated in the STMicroelectronics 55-nm bipolar-cmos (BiCMOS) technology, demonstrating a return loss greater than 10 dB across the 50-160-GHz frequency range, an attenuation greater than 18 dB below 5 GHz, and a minimum insertion loss at 90 GHz of 0.55 dB. To prove the performance of the proposed solution, human body model (HBM) and charge device model (CDM) events were simulated at the input of the 3-dB coupler, showing that the proposed architecture effectively protects against these events while minimally impacting the RF path.

Next generation high-speed wireline and optical communications will target single lane data rates over 200Gb/s. For this, the generation and transmission of $\gt100$ Gbaud PAM-4 is a key step. Recent transmitters in advanced CMOS and FinFET nodes [1,2] provide extensive transmit-side FFE capabilities at respectively 64 and 56Gbaud. Speed limitations in these technologies will make the transition to $\gt100$ Gbaud a challenge. Alternatively, InP-based multiplexers like [3] manage to reach $\gt100$ Gbaud easily. They also offer the possibility to create high-swing output drivers, necessary to efficiently drive optical modulators. However, InP solutions lack the ability to introduce more complex equalization of the signal. BiCMOS based transmitters like in [4], enable the integration of more complex circuits with respect to InP technologies, are capable to deliver high signal swings required for optical drivers and promise increased bandwidth compared to CMOS/FinFET. This paper presents a 120Gbaud PAM-4 TX incorporating a 7-tap FFE in a 55nm BiCMOS technology. The advantage of the presented FFE architecture is the efficient use of both digital and analog delay structures to obtain $\gt100$ Gbaud operation with a large amount of filter taps in a compact configuration.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

International audience; This paper describes two fully-integrated transfer switches designed for in-situ reflectometers and Built-In Self-Test applications (BIST) in the 140 to 220 GHz band (G-band). The proposed switches were designed in the STMicroelectronics 55-nm BiCMOS technology using the Single-Shunt and the Double-Shunt topology, respectively. In the 140 to 195 GHz frequency range, the Double-Shunt Transfer Switch shows an isolation between 27 and 46 dB, and an insertion loss between 5 and 7 dB. Compared to the Single-Shunt Transfer Switch, the double shunt switch presents a much better isolation while having a quite comparable insertion loss and area overhead. To the best of our knowledge, the proposed switches are the first fully integrated transfer switches in BiCMOS or CMOS technologies.

International audience; A non-closed-form general mathematical model for CMOS distributed amplifier (DA) for broadband applications is presented. Contrary to the artificial transmission line (TL) assumption made in the conventional analytical models, the proposed model treats the DA as a discrete set of cells connected together, and hence considers propagation and mismatch between inter-cells. This approach provides designers with a much more accurate first sizing of the DA compared to conventional ways and, as a result, leads to a reduced design time and complexity. The model enables both quantitative and qualitative analysis of a DA, for the purpose of aiding the designers in predicting the relations between DA performance and its multi-design parameters, especially in the context of non-uniform designs. In addition, it is well suited to Computer-Automated Design (CAutoD), to help in achieving designs having a given set of performance goals. The validation of the model is demonstrated on two designs, by a comparison with simulations done in Keysight's ADS tool and using STMicroelectronics' 55-nm SiGe BiCMOS design kit. First design is inspired from an already published non-uniform DA design while second one proposes a 100-GHz bandwidth CMOS uniform DA with 8 dB of power gain, after using it in a CAutoD process.