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A coarse‐fine dual‐loop digital low dropout regulator (DLDO) having a binary weighed transistor array in the coarse loop and a 1‐bit ΔΣ modulator in the fine loop is proposed. Compared with the conventional DLDO, the proposed architecture significantly reduces hardware complexity and alleviates matching requirement, enabling a robust DLDO design for low‐voltage phase‐locked loops. The proposed DLDO designed in 65 nm CMOS generates a noise‐shaped output voltage whose peak value is <1 mV with the load current ranging from 100 μA to 6 mA. [ABSTRACT FROM AUTHOR]