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We report a clock/logic/input structure for nanomagnet logic (NML) that implements a two-input slant-based OR gate with both clocking and input programming through current pulses. The clock line is a copper conductor embedded in a Si substrate with CoFe as a flux concentrator. Inputs are implemented with overlaid and dedicated bias lines. The programmability of such inputs allows us to test the same NML device for all possible input combinations. Results are determined by magnetic force microscopy. This scheme is easy to fabricate and can control thicker (20–30 nm) input nanomagnets. Close proximity of bias lines in such a structure allows us to investigate the effect of overlapping bias fields. We also report micromagnetic simulations that relate the slant in the output magnet to the dimensions of the input nanomagnets required to effect proper logic operation. [ABSTRACT FROM AUTHOR]

We report an electric, field-coupled input scheme for nanomagnet logic (NML). Furthermore, input structures are integrated with CMOS compatible clock structures for NML. This paper describes the controlled switching of the magnetization state of a nanomagnet by applying a locally generated biasing field to a device that has been placed in a 0°/metastable state by a clad, current carrying clock line. Fringing fields from the set device can then change the state of another, adjacent nanomagnet. This scheme can serve as an electric–magnetic interface between CMOS and an NML circuit. [ABSTRACT FROM PUBLISHER]

We present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance. [ABSTRACT FROM PUBLISHER]

Nanomagnet logic (NML) has received increasing attention as an alternative information processing technology given the potential for low energy dissipation, a relatively advanced experimental state of the art, and intangibles such as inherent radiation hardness and nonvolatility. In order to facilitate the integration of NML-based circuits with transistor-based circuits, a magnetic–electrical interface (MEI) is needed. This paper focuses on the output portion of MEI design, i.e., converting signals from the magnetic domain to the electrical domain. The basic idea of an MEI output is to employ fringing fields from an NML device to set the magnetization state of the free layer of a magnetic tunnel junction. A detailed study of four different MEI output designs is presented which considers metrics such as the clock energy required to set the output state, the magnetoresistance ratio, etc. Simulation-based analysis reveals the pros and cons of each design. A design where multiple NML devices (i.e., free layers) share a large synthetic antiferromagnet is most promising based on our simulation-based, quantitative analysis. [ABSTRACT FROM PUBLISHER]

The nanomagnet logic (NML) devices considered here are variants of proposed components for the edge-driven, quantum-dot cellular automata device architecture, where the position of electrons on quantum dots was suggested as a mechanism for representing binary state. To control NML circuit components (e.g., gates and lines), to date, externally generated magnetic fields have served as a clock. The clock is used to make the magnets in a circuit ensemble transition to a metastable state, so fringing fields from individual devices can set the state of a neighboring device in accordance with a new input. However, such a clocking scheme is obviously not extensible to chip-level systems. For NML to be a viable candidate for digital systems, a mechanism for simultaneously modulating the energy barriers of a group of devices must be implemented “on-chip,” and guarantee unidirectional dataflow from circuit input to circuit output. We have experimentally demonstrated a CMOS-compatible clock, and used it to reevaluate all of the NML constructs required for a functionally complete logic set. All possible input combinations to said constructs were successfully considered. Experiments were designed to promote unidirectional dataflow. [ABSTRACT FROM PUBLISHER]

We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets. [ABSTRACT FROM PUBLISHER]

We present simulations of, and design alternatives for, an interface between nanomagnet logic (NML) and electrical circuitry. We propose using the fringing fields from a nanomagnet to help set the state of the free layer of a magnetic tunnel junction (MTJ). Our first magnetic–electrical interface design (MEI-1) assumes an MTJ stack layout, commonly seen in commercial magnetoresistive random access memory (MRAM). Our second design (MEI-2) is also based on a traditional MRAM process flow, but layers of the MTJ are deposited in reverse order. In MEI-2, the NML devices have the same thickness as the MTJ free layer. Simulations for MEI-2 suggest that the layer thickness and size are important design parameters, when considering realistic implementations of this MEI. By comparison, MEI-2 is applicable for the present process technology, while MEI-1 would be more easily fabricated with further technology development. [ABSTRACT FROM PUBLISHER]