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We report a clock/logic/input structure for nanomagnet logic (NML) that implements a two-input slant-based OR gate with both clocking and input programming through current pulses. The clock line is a copper conductor embedded in a Si substrate with CoFe as a flux concentrator. Inputs are implemented with overlaid and dedicated bias lines. The programmability of such inputs allows us to test the same NML device for all possible input combinations. Results are determined by magnetic force microscopy. This scheme is easy to fabricate and can control thicker (20–30 nm) input nanomagnets. Close proximity of bias lines in such a structure allows us to investigate the effect of overlapping bias fields. We also report micromagnetic simulations that relate the slant in the output magnet to the dimensions of the input nanomagnets required to effect proper logic operation. [ABSTRACT FROM AUTHOR]

We report an electric, field-coupled input scheme for nanomagnet logic (NML). Furthermore, input structures are integrated with CMOS compatible clock structures for NML. This paper describes the controlled switching of the magnetization state of a nanomagnet by applying a locally generated biasing field to a device that has been placed in a 0°/metastable state by a clad, current carrying clock line. Fringing fields from the set device can then change the state of another, adjacent nanomagnet. This scheme can serve as an electric–magnetic interface between CMOS and an NML circuit. [ABSTRACT FROM PUBLISHER]

In this paper a 1-bit full adder realized in perpendicular nanomagnetic logic (pNML) is presented for the first time. The theory of NML with perpendicular magnetic anisotropy is introduced illustrating the great benefit of the universal majority decision. The working principle of complex logic circuits is experimentally demonstrated utilizing the presented full adder. Partial focused ion beam irradiation is used to control the anisotropy locally and tailor the magnetic behavior of the nanomagnets. A full adder structure consisting of 3 majority gates and 4 inverters is realized on an area of 17 um^2. Global, alternating field pulses with constant amplitude are used as power clock. MFM measurements demonstrate the functionality of the structure and the validity of the introduced theory. [ABSTRACT FROM AUTHOR]

We present the design and simulation of systolic information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic or oNML). The designed circuit can identify instances of a preprogrammed bit sequence in streaming data. The systolic architecture 1) exploits unique benefits of the oNML device architecture such as nonvolatility and inherently pipelined logic with no memory overhead for holding the bits in the pipeline and 2) mitigates less desirable features of oNML such as nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor. The designed layout is verified and analyzed by micromagnetic simulations. We quantify how the performance and energy of oNML information processing hardware compares to CMOS equivalents and conclude that the initial oNML design (including the overhead of magnetic field generation) is about an order of magnitude more power efficient at essentially iso-performance. [ABSTRACT FROM PUBLISHER]

Nanomagnet logic (NML) has received increasing attention as an alternative information processing technology given the potential for low energy dissipation, a relatively advanced experimental state of the art, and intangibles such as inherent radiation hardness and nonvolatility. In order to facilitate the integration of NML-based circuits with transistor-based circuits, a magnetic–electrical interface (MEI) is needed. This paper focuses on the output portion of MEI design, i.e., converting signals from the magnetic domain to the electrical domain. The basic idea of an MEI output is to employ fringing fields from an NML device to set the magnetization state of the free layer of a magnetic tunnel junction. A detailed study of four different MEI output designs is presented which considers metrics such as the clock energy required to set the output state, the magnetoresistance ratio, etc. Simulation-based analysis reveals the pros and cons of each design. A design where multiple NML devices (i.e., free layers) share a large synthetic antiferromagnet is most promising based on our simulation-based, quantitative analysis. [ABSTRACT FROM PUBLISHER]