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This paper presents a receive chain for very-high bit rate (VHBR) communication over a short range 13.56MHz inductively coupled interface, using multi-bit-per-symbol phase-shift keying (PSK) as proposed for the ISO14443 VHBR amendment. A data rate of up to 13.56Mbps is achieved. The receiver consists of an analog front-end IC followed by an FPGA-based digital baseband processor (DSP). The analog front-end IC recovers the carrier from the antenna signal and performs PSK demodulation using an 8-bit time-to-digital converter (TDC). It consumes 100µA in the 13.56Mbps data rate mode. The FPGA-based DSP's main functions are symbol clock recovery in a closed-loop with the analog front-end as well as adaptive equalization. Target bit error rates of below 2·10−4 were achieved for transmitted field strengths above 1.2A/m. [ABSTRACT FROM PUBLISHER]