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In sub/near-threshold operation, SRAMs suffer from considerable bitline swing degradation when the data pattern of a column is skewed to ‘1’ or ‘0’. The worst scenarios regarding this problem occur when the currently read SRAM cell has different data compared to the rest of the cells in the same column. In this work, we overcome this challenge by using a column-based randomization engine (CBRE). This CBRE circuit randomizes data stored to SRAM. This makes distribution of “1” and “0” in each column close to 50%, significantly increasing bitline swing. To further improve the bitline swing, we employ bitline boost biasing and dynamic bitline keeper schemes. Based on the mentioned techniques, we fabricated a 256 rows × 128 columns (32 Kb) 8T SRAM array in 65 nm CMOS technology. In our silicon measurement, the SRAM array shows successful 200 mV operation at room temperature, where energy consumption and access time are 1 pJ and 2.5 s, respectively. [ABSTRACT FROM PUBLISHER]

This brief presents a negative bias temperature instability (BTI)/positive BTI-aware write-wordline (WWL) voltage control technique for improving degraded cell stability of half-selected cells without extra power consumption. After BTI aging, the proposed lowering WWL voltage recovers the degraded cell stability without scarifying the write margin. Finally, we also present a sample circuit implementation of the proposed WWL voltage control scheme. [ABSTRACT FROM PUBLISHER]