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This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- [micro]m CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation. Index Terms--I/O, multiplexer, MUX, serdes, serializer.

The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture. Index Terms--Clock distribution, clock recovery, high-speed I/O, phase-locked loops.

This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of [+ or -] 10 kHz. The linearity at the range of 27 MHz [+ or -] 10 kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 [mm.sup.2] in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip. Index Terms--Clock recovery, clock synchronization, digital control crystal oscillator (DCXO), flying adder, MPEG2, phase-locked loop (PLL), voltage-control crystal oscillator (VCXO).

Synthesizers for the generation of frequency- or phase-modulated signals are required in communications, sensing, and many other fields and applications. The widespread use of phase-locked loops (PLLs) as major building blocks in current systems requires accurate models and methods for eliminating the influence of statistical and deterministic errors in the synthesized signals. We propose a novel iterative phase-error-measurement and -compensation procedure applicable in PLL-based synthesizers, for which the mathematical background is presented, and a detailed algorithmic description is given in this work. From a mathematical PLL system model and its response to a periodic excitation by the modulating signal, a method for measuring the instantaneous output signal phase and the actual transfer function of the PLL is derived. It is shown how this knowledge can advantageously be used for pre-distorting the synthesizer input signal to eliminate deterministic errors and to obtain an accurate output phase curve. Index Terms--Chirp radar, frequency synthesizers, phase-locked loops (PLLs), phase measurement.