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A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 /spl mu/W, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70/spl deg/C. Chip area (including scribe line) is 55.5 mm/sup 2/ in a 0.8 /spl mu/m N-well double-metal single-poly CMOS process with implanted capacitors.

A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is integrated in a mature 0.7-/spl mu/m BiCMOS technology, has a die size of 54 mm/sup 2/, and dissipates 2 W with MSN code or 1.5 W with PR4 code at 4.5-V supply and 200 MSample/s.

A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mW

This paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 /spl mu/m CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9/spl times/1.6 mm/sup 2/) 2.1 GHz /spl Sigma//spl Delta/ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth.

A fully-integrated PRML read/write IC with digital adaptive FIR operating up to 450 Mbit/s is presented, The chip implements an EPR4 Viterbi detector as well as a digital servo. The device is integrated in a 0.35 /spl mu/m BiCMOS technology, has a die size of 11.44 mm/sup 2/ (step and repeat) and dissipates 1.3 W (in read mode) at 450 Mbit/s.

A low voltage, low power CMOS single chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 AD-PCM coder/decoder, a Burst Mode Logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. It can be easily interfaced with standard microcontrollers through a parallel interface. It can operate from a 2.7 V minimum supply with operative and stand-by power consumptions of 35 mW and 25 /spl mu/W, respectively. Maximum operative supply is 5.5 V. Chip area is 55.5 mm/sup 2/ in a 0.8 /spl mu/ N-well CMOS process.