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Tissue nanotransfection (TNT) is an electromotive gene transfer technology that was developed to achieve tissue reprogramming in vivo. This protocol describes how to fabricate the required hardware, commonly referred to as a TNT chip, and use it for in vivo TNT. Silicon hollow-needle arrays for TNT applications are fabricated in a standardized and reproducible way. In

Cell-on-a-Chip (COC) can be utilized to get a preliminary analysis of the drug development for reducing the usage of experimental animals. Several strategies of surface modification in microchannel have been used to make the cells attach to the surface that increases the complexity of the COC chip fabrication. In the study, we propose a COC platform which has a reversible package design and a simple cell seeding process. Cells attach to a circular glass slide without any modification, and it provides the possibility of the duplex cells analysis in a chip. Using this COC platform, the function and harm of the new cancer drugs can be evaluated efficiently.

Nanofluidic devices are becoming increasingly critical for medical, chemical and biological applications. In this paper, a 2D Polycarbonate (PC) nanofluidic chip was fabricated by hot embossing and thermal bonding method. In this paper, the effect of the hot embossing parameters on the replication precision of 2D PC nanochannels was investigated by finite element method. To increase the bonding rate of the chip, the parameters of the thermal bonding process were optimized. Under the optimized parameters the 2D PC nanofluidic chip was successfully fabricated. The results show that the replication precision of the nanochannels can be as high as 97% and the bonding rate of the chip can be 96%. The fluorescent images demonstrate that there is no block and leakage through the whole microchannels and nanochannels. It is expected that this fabrication method has great potential to fabricate 2D nanofluidic chip with low cost and high precision.

The aim of the development of ASIC v3 was to implement the ROIC functionality of the SMARTImplant system using ultra-thin chip fabrication technologies. As presented in Chapter 2, the flexible substrate model of the implant was designed so as to have only a flexible sensor electrode tip implanted inside the body and the rest of the implant electronics placed on the circular pad outside. One of the most important issues with this setup is the resistance of the wires between the electrodes and the readout chip, which have a length of almost 12 cm.

This presentation covers chip fabrication services on SOI devices in Japanese universities, and demonstrate ultra-low energy cryptographic engine design as an example of SOI chip fabrication. VLSI Design and Education Center (VDEC) has established in 1996 as a inter-university facility at the University of Tokyo. VDEC provides chip fabrication services, major EDA tools, and seminars for chip designs to Japanese universities for academic purposes. Through the VDEC activities, we have provided several chip fabrication services on SOI, including 0.15um FDSOI, 0.6um SOI, 0.35um BiCMOS SOI, 28nm FDSOI, and 65nm FDSOI. As a design example of 65nm FDSOI, namely, SOTB, This presentation will describe ultra-low energy ECDSA design.

To improve the efficiency of nano-electronic device fabrication, a new method named floating electrical potential assembly is proposed to realize large-scale assembly of Cu/CuO nanowires. The simulation of floating electrical potential distribution on the micro-electrode chip is performed by COMSOL software, and the simulation result shows that the coupled electrical potential on the floating drain electrodes is very close to the original electrical potential applied on the gate electrode, which means that the method can provide di-electrophoresis (DEP) force for all the electrode pairs at one time, thus realizing large-scale assembly at one time. With Cu/CuO nanowires well dispersed and micro-electrode chip fabrication, nanowires assembly experiments are performed and the experimental results show that Cu/CuO nanowires are assembled at hundreds of micro-electrodes pairs at one time, and the success rate of nanowires assembly also reaches 90%.

The development of polydimethylsiloxane-based microfluidic devices with integrated controlling components has led to the translation of many bench-top biological processes to microdevice platforms. While many biomedical scientists recognize the applicability of microdevices to their research, their lack of engineering background and training in computer-aided design (CAD) makes them unable to design the desired microchips using AutoCAD software, which is the universal first step for chip fabrication. In this work, we used the .NET platform to develop a user-friendly AutoCAD add-on feature that includes the ability to create channels, loops, valves, and punches, as well as channel to loop connections, valve to channel connections, valve to loop connections, channel to channel connections, and punch to channel connections. This add-on feature greatly simplifies the process of AutoCAD drawing, which allows people not familiar with AutoCAD to easily learn to use the add-on. For testing purposes, we used the add-on to draw a series of two-layer microchips designed to synthesize luciferase using a coupled transcription-translation system with different capacities. The AutoCAD files for the microfluidic designs were then sent to the Stanford Microfluidics Foundry for chip fabrication. Our results show that the quantity of luciferase produced on the chip is proportional to the capacity of the reaction loop.

Ultrathin chip fabrication is an enabler of high-performance hybrid systems-in-foil (HySiF) for flexible electronics as well as 3D IC's. Minimum chip thickness, exact thickness control, uniformity and reproducibility as well as smoothness of chip surfaces and edges are important requirements in both applications. Most commonly, thinning is arranged at wafer level prior to chip singulation, which is classified as a subtractive method. In contrast, an additive thin-chip technology called ChipFilm™ is presented here, meeting all those requirements. It is shown that by using ChipFilm™ both wafer-level and chip-level thinning are feasible.

As the technology advances, a growing number of biomedical microelectromechanical systems (bio-MEMS) research involves development of lab-on-a-chip devices and micrototal analysis systems. For example, a portable instrument capable of biomedical analyses (e.g., blood sample analysis) and immediate recording, whether the patients are in the hospital or home, would be a considerable benefit to human health with an excellent commercial viability. Digital microfluidic (DMF) system based on the electrowetting-on-dielectric (EWOD) mechanism is an especially promising candidate for such point-of-care systems. The EWOD-based DMF system processes droplets in a thin space or on an open surface, unlike the usual microfluidic systems that process liquids by pumping them in microchannels. Droplets can be generated and manipulated on EWOD chip only with electric signals without the use of pumps or valves, simplifying the chip fabrication and the system construction. Microfluidic operations by EWOD actuation feature precise droplet actuation, less contamination risk, reduced reagents volume, better reagents mixing efficiency, shorter reaction time, and flexibility for integration with other elements. In addition, the simplicity and portability make the EWOD-based DMF system widely popular in biomedical or chemical fields as a powerful sample preparation platform. Many chemical and biomedical researches, such as DNA assays, proteomics, cell assays, and immunoassays, have been reported using the technology. In this paper, we have reviewed the recent developments and studies of EWOD-based DMF systems for biomedical applications published mostly during the last 5 years. © 2014 Springer-Verlag Berlin Heidelberg.

Since launching the project to get extreme ultraviolet lithography (EUVL) ready for production, we focused on two issues: test chip fabrication down to a half pitch (hp) of 28 nm to assess an applicability of EUVL to the fabrication of logic devices (BEOL test chip); and the manufacturability of EUVL, for which we used a special PL test site to assess the electrical yield. Furthermore, we examined the potential of EUVL for device fabrication at sizes beyond hp 24 nm.

Silicon-on-insulator (SOI) is a wafer substrate technology with potential to fabricate ultra-thin silicon layers and thus ultra-thin chips. The high cost of SOI wafers and technical difficulties to derive ultra-thin chips from SOI substrates so far have hindered the industrial exploitation of SOI technology for thin chip manufacturing. This chapter provides an overview of the present and past SOI technologies, a discussion about the technical difficulties in thin-chip fabrication based on SOI, and a former industrial approach as a related example.

The sections in this article are Introduction Multiplexed Polymerase Chain Reaction from A Single Copy DNA using Nanoliter-volume Microchamber Array PCR Microchamber Array Chip System Microchamber Array Chip Fabrication Sample Loading with a Nanoliter Dispenser Multiplexed Detection of Different Target DNA on a Single Chip On-chip Quantification of Amplified DNA On-chip Cell-free Protein Synthesis using A Picoliter Chamber Array Cell-free Protein Synthesis Chip Fabrication Cell-free Protein Synthesis using a Microchamber Array High-throughput Single-cell Analysis System using Pico-liter Microarray Single-cell Microarray Chip Fabrication Pico-liter Microarray for Single-cell Studies Single-cell Microarray System for Analysis of Antigen-specific Single B-cells Conclusions Acknowledgments

With the dramatic increase in mask costs, multi-project wafers have became an attractive choice for low-volume chip fabrication. By using the same set of masks to fabricate a number of different chips, the mask-set cost is amortized among different chip providers, leading to significant cost reduction especially for chip prototyping. In this paper, we present a new algorithm for reticle floorplanning with wafer yield guarantees. The previous approach of Kahng et al. considers optimizing both the reticle area and the wafer yield, leading to suboptimal solutions with no yield bounds. By contrast, we consider the yield as a constraint and optimize the area accordingly. We characterize yield constraints and provide a mechanism through which yield can be incorporated into an optimal-area packer. The incorporation of yield constraints prunes large parts of the search space of the optimal-area packer, leading to runtime-efficient optimal-area floorplans with guaranteed yields. Empirical results demonstrate that our approach dominates previous results, i.e., we give floorplans that consume less area and have higher die yields. For the 10 benchmarks, we achieve a yield improvement of 14% with an area reduction of 2%.

In this paper we discuss some design, implementation and test issues, with respect to the development of the RAPS01 chip in the framework of the Radiation Active Pixel Sensors (RAPS) INFN project. The project aimed at verifying feasibility of smart, high-resolution pixel arrays with a fully standard, submicron CMOS technology for particle detection purposes. Layout optimization of the pixel, including sensitive element and local read and amplification circuits has been carried out. Different basic pixel schemes and read-out options have been proposed and devised. Chip fabrication has been completed and test phase is now under way: to this purpose a suitable test environment has been devised and test strategies have been planned.

This paper reviews the chip fabrication services for universities in North America and European countries. One feature of these services is the adoption of a chip fabrication system (called Multiproject Chip) that makes it possible for users at universities to fabricate chips at an extremely low cost. The key idea of the multiproject chip system is that sharing a chip or a wafer among several projects makes it possible to greatly reduce manufacturing costs. The paper covers MOSIS (USA), CMC (Canada), CMP (France), EIS (Germany) and Eurochip (Europe) services. Those services have clearly been making great contributions to increasing the expertise in LSI design at universities.

The paper presents a method for the estimation of product reliability based on tests performed at the chip fabrication stage, which is time and money saving for manufacturer. It relates to the manufacture of automotive rectifier diodes in DO21 case. The aim was to establish to a correlation between the pressure resistance of chips and the results of standard reliability test, RTV (rapid thermal variations).

A versatile micro fluidic device "Biochemical IC Family" based on the concept of IC chip-set family has been proposed and developed by the authors. Several types of biochemical IC containing multiple micro fluidic devices such as reactors, concentrators and one-way valves have been already developed and we have demonstrated that a luminous enzyme of firefly was synthesized by using these chips. Since all chemical fluids were supply by the external pumps in the past experiment, the micro pump chip and switching valve chip are demanded for total IC family. In this research, new chips to handle chemical fluid were first fabricated successfully and basic performance was verified experimentally. Shape memory alloy (SMA) micro actuator was utilized for micro actuation. A new micro stereo lithography process (Hybrid IH Process) to make 3D composite structures consisting of UV polymer and other micro parts was developed and was utilized for total chip fabrication. The micro pump chip succeeded to supply chemical liquids through the connected chips. On the other hand, the micro switching valve chip changed reaction passes quickly. By using these biochemical IC chips, a new era where various kinds of reaction systems can be constructed by chemists in their own laboratory will come.

Versatile micro fluidic device "Biochemical IC Family" based on the concept of family IC chip-set has been proposed and developed by the authors. Several types of biochemical IC containing multiple micro fluidic devices such as reactors, concentrators and one-way valves have been developed. A luminous enzyme of firefly was synthesized by using these chips. New chips to handle chemical fluid were first fabricated successfully and basic performance was verified experimentally. Shape memory alloy (SMA) micro actuator was utilized for micro actuation. New micro stereo lithography (Hybrid IH Process) to make 3D composite structure consisting UV polymer and other micro parts was developed and was utilized for total chip fabrication. The pump chip succeeded to flow chemical liquids through the connected chips. The switching valve chip changed reaction passes quickly. By using these biochemical IC chips, new era in where various kind of reaction system can be constructed by the chemists in their own laboratory will come.

We fabricated the optimized SMA micro pump chip applicable to both liquids and gases. The measured maximum flow and pressure for water were 12 µl/min. and 25 kPa, respectively. And the flow and pressure for air were 11 µl/min. and 5 kPa, respectively. Moreover, the micro pump satisfied insensitive ability to gas bubbles and self-priming. This performance was realized by improving the check valves, the chamber and the SMA actuator design. Our original 3D micro fabrication process named “Hybrid IH process (micro stereo lithography)” to hybridize various micro solid parts with UV-polymer structure was utilized for chip fabrication. Therefore, their packaging without leakage was made successfully.

International audience; This paper details the history and development of MPC (Multi-Project Chip) Services available in various countries. The CMP French Service is also used to exemplify a few basic principles that should govern the management of such Services. Some of these principles have evolved during the last 10 years, especially when considering University oriented chip fabrication. Also the expected development of different technologies is addressed, to assess which of these technologies should be offered.

Large scale integration offers the possibility of very low-cost digital circuits. However, to realize fully the cost potential in LSI, several problems must be solved, one of which is the time and cost involved in preparing, by conventional techniques, masks for LSI chip fabrication. To facilitate mask generation, an artwork generator system has been developed. The system, comprised of a small artwork generator of high capability and a language structure which allows for compact description of chip features, has demonstrated itself capable of substantial savings in mask generation time and cost.

Most chip-counting algorithms use the Pythagorean theorem; in effect, a grid of chips is superimposed over the wafer, and the radial distance from the center of the water to the outermost vertex of each potential chip site is computed. Only those chips are counted for which this radial distance is less than the effective radius of the wafer. To minimize edge-related chip loss, chip fabrication is usually restricted to the area of the wafer that lies within a containment circle of a radius 1-2 mm than the actual wafer radius. A simple and reasonably accurate algebraic expression is presented that explicitly relates the number of chips per wafer to the wafer diameter and to the geometric parameters that characterize the chip, i.e. the edge-length, the kerf plus pad cage dimension and the aspect ratio. The expression is applied to determining the size of chip for which the product of chips per wafer and circuits per chip is maximized for a given wafer diameter. >

Since the 1960s, electronic components that make up digital systems have been packaged as tiny integrated circuits (ICs) or chips. There has been steady progress since that time in making the components smaller and thereby packing more components per chip. This has led to several generations of IC devices, from small-scale integration (SSI), with only a couple of components per chip, to medium-scale integration (MSI) and large-scale integration (LSI), with tens of thousands of components per chip (Myers 1980). As a result of improvements in the technology of chip fabrication, achievable circuit densities continue to grow higher. The present level of density extends into very-large-scale integration (VLSI).