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We compared the electrical characteristics, including mobility and on -state current Ion, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

A sputtered titanium nitride (TiN) metal gate has systematically been investigated, and the dependences of TiN work function (TiN) and device performance on nitrogen gas flow ratio [RN=N2/(N2+Ar)] in sputtering and rapid thermal annealing (RTA) temperature (TR) are clarified. It is experimentally found that TiN slightly decreases from 4.87 to 4.78 eV with increasing RN from 17 to 83%, and it markedly decreases with increasing TR. The analysis of the electrical characteristics of fabricated metal–oxide–semiconductor field-effect transistors (MOSFETs) shows that the optimal RN range is 17–50%, and a higher RN offers a lower Vth owing to the lower TiN. The origin of TiN decrease with increasing RN and TR is discussed. The obtained results indicate that TiN can be controlled by sputtering and RTA conditions, and are very useful for setting the appropriate Vth for lightly doped channel devices such as a FinFET.

This paper presents the fin-height controlled TiN-gate FinFET CMOS technology based on the experimental carrier mobility data. The good current matching by tuning the N-channel fin-height and the excellent transfer performance in the fabricated TiN-gate CMOS inverter are demonstrated. The developed technologies are attractive to materialize the high-performance FinFET CMOS circuits.

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phiTiN) slightly decreases with increasing nitrogen (N2) gas flow ratio, RN=N2/(Ar+N2) in the sputtering, from 17% to 100%. The experimental threshold voltage (Vth) dependence on the RN shows that the more RN offers the lower Vth for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different RN showed that the more amount of nitrogen is introduced into the TiN films with increasing RN, which suggests that the lowering of phi TiN with increasing RN should be related to the increase in nitrogen concentration in the TiN film. The desirable Vth shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n+ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication

This paper presents, for the first time, the experimental electron mobility in FinFETs with a (111) channel surface fabricated by the orientation-dependent wet etching. The maximum electron mobility (ueff) is around 300-cm2 /V-s, which is close to that in the (111) bulk MOSFETs. Moreover, the value of ueff is comparable or better than the reported ones in the usual FinFETs with a (110) channel surface prepared with careful surface treatments. This result indicates that the quality and channel surface roughness of the Si-fins by the orientation-dependent wet etching are much better than those fabricated by the conventional reactive ion etching (RIE) process.

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.

The effectiveness of amorphous metal gate (MG) in suppressing low-frequency noise (LFN) for FinFETs has been thoroughly investigated. It was demonstrated that the amorphous TaSiN MGs with various atomic compositions provide flexible tuning of threshold voltage (V t ) as well as small V t variability, namely AVt. It was found that the TaSiN-MG FinFETs exhibit drastic reduction of LFN in comparison to the poly-crystalline TiN MG case. Modelling by 3D-TCAD reveals that work function variation (WFV) of the MG has a significant impact on LFN generation. Suppression of A Vt and LFN is highly beneficial to conduct further scaling of analog/digital components in SoC.

Fluctuation in drain induced barrier lowering (DIBL) has been investigated in detail for FinFETs with regard to work function variation (WFV) in the metal gates (MGs). The FinFETs with a polycrystalline TiN MG exhibit significantly larger fluctuation in DIBL than that for an amorphous TaSiN MG because of the WFV. The granular WFV of TiN was modeled using 3D TCAD simulation. By reproducing the DIBL fluctuation caused by the WFV, mechanism of how the WFV causes the DIBL fluctuation is discussed.

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

We report guidelines for symmetric threshold voltage (V th ) in double gate (DG) tunnel FinFETs (tFinFETs) with single and dual metal gate electrodes. To realize the symmetric V th =±0.2V, the work function difference (ΔΦ m ) of each gate electrode in n- and p-type tFinFETs with a nondoped Si channel must be 1.34 eV, indicating that tuning the effective work functions in the dual metal gates is difficult. By adding Ge in the channel, the work function required in Ge-channel p-tFinFETs can be reduced to 4.46 eV, furthermore, ΔΦ m required to realize a symmetric V th in n- and p-type tFinFETs can be as small as the minimum value of 0.28 e V. This result means that a symmetric V th is realized in realistic dual metal gate materials by adding Ge. By using our independent DG tFinFETs with a novel source profile, a symmetric V th can be realized in a single metal gate in a Ge channel.

Influence of work function (WF) uniformity of metal gates (MGs) on current-onset voltage (COV) fluctuation is investigated in detail for MG FinFETs. In addition to significantly suppressed variability of threshold voltage (Vt) itself, FinFETs with an amorphous TaSiN MG exhibit smaller COV fluctuation than that with a polycrystalline TiN MG. It is revealed that the COV variability is caused by the potential non-uniformity in the channel due to the WF variation of the poly grains and is effectively improved using the amorphous MG.

Amorphous TaSiN metal gates (MGs) are successfully introduced in FinFETs to suppress work function variation (WFV) of the MG, which is a dominant contributor to threshold voltage (V t ) variability of the undoped channel MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces V t variation drastically and records the smallest A Vt value of 1.34 mVμm reported so far for MG FinFETs. Interface traps also become a dominant A Vt origin in the case of well-suppressed WFV using the amorphous M G. The WFV suppression is also effective to reduce trans-conductance (G m ) variability which will be a dominant source of on-current (I on ) variability in 14 nm technology and beyond.

The tri-gate (TG)- and double-gate (DG)-type poly-Si fin-channel split-gate flash memories with a thin n+-poly-Si floating-gate (FG) have successfully been fabricated, and their electrical characteristics including the variations of threshold voltage (Vt) and S-slope have been comparatively investigated. It was experimentally found that better short-channel effect (SCE) immunity, smaller V t variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. Moreover, it was also confirmed that over-erase is effectively suppressed by split-gate structure.

We experimentally investigated the device performance of n+- poly-Si/PVD-TiN stacked gate FinFETs with different H fin 's. It was found that mobility enhances in the tall H fin devices due to the increased tensile stress. However, as L g decreases, I on for tall H fin case becomes worse probably due to high R sp . It was also confirmed that V th variation increases with increasing H fin due to the rough etcing of fin sidewall.

T R dependence of the electrical characteristics have systematically been investigated by fabricating PVD-TiN gate FinFETs. It was found that optimal T R is 915 °C for setting symmetrical V th with a higher I ON and the smallest σV th . It was also confirmed that carrier mobilities are independet of T R and comparable to those in the case of n+-poly-Si gate. The n+-poly-Si capping on PVD-TiN gate is very useful to set symmetrical V th for undoped FinFETs without mobility degradation.

We have demonstrated the effect of the resistivity reduction of the ALD-TiN film using TDMAT precursor by modifying the NH 3 process (both initial exposure and PDA processes). It was found that the resistivity of the ALD TiN was significantly reduced by extending t NH3 and increasing T PDA by 700°C. Moreover, by employing the NH 3 PDA, an increase in TiN peak intensity was detected from Ti 2p by XPS analysis and Ti : N ratio of approximately 1∶1 was achieved. As a result of the evaluation of the electrical characteristics of TiN-gate MOSFETs, superior performance was achieved in the case of ALD TiN.

The V t variability in scaled FinFETs with gate length (L g ) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (T ox ) dependence of V t variation (VTV), the gate-stack origin, i.e., work-function variation (WFV) and gate oxide charge (Q ox ) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (T Si ) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the V t of multi-FinFETs with the same gate area reduces with increasing the number of fins.

Variability of the TiN FinFET SRAM cell performance is comprehensively studied. It is found that the static noise margin (SNM) variation of the SRAM cell is due to the V th variation of FinFETs caused by the work function variation (WFV) of the TiN metal-gate. It is experimentally demonstrated that the V th -controllable independent-double-gate (IDG) FinFET technology successfully compensates not only the random variation but also the systematic variation problems in SRAM performance. As a result, IDG-FinFET technology enables 0.5 V SRAM operation with a high cell stability.

It is well known that the PVD TiN is a promising gate material to set symmetrical threshold voltage (V th ) for nondoped channel FinFET CMOS thanks to its midgap work function [1–4]. One of the most important issues in the TiN gate FinFET fabrication is the TiN gate formation especially the TiN etching on the sidewalls of the tall fin channels by using conventional RIE. Hence, an isotropic TiN etching technique is strongly required in the tall FinFET fabrication. In this paper, we experimentally investigate nanoscale TiN side-etching by wet process and demonstrate the FinFET CMOS fabricated by using the developed TiN wet etching technique.

Recently, extreme scaling of the MOSFET causes a significant increase in the variation and reduction in CMOS circuit stability. Double-gate (DG) FinFETs with metal-gates (MGs) have been recognized as the most promising candidate for the future nano-scale devices [1–2]. However, variability of the FinFET occurs (Fig. 1) and its origin has not been understood well. Possible sources of the V th variation are fluctuations of gate-length (ΔL g ), fin-width (ΔT Fin ), oxide thickness (ΔT ox ), and work function (ΔΦ m ). On-current variation (ΔI on ) is caused not only by ΔV th , but also by parasitic resistance variation (ΔR p ) and ΔT ox . In this paper, we thoroughly investigate the variation in the TiN MG FinFET.

TiN gate FinFET SRAM half-cells with different s-ratios from 1-3 have successfully been fabricated by using the orientation dependent wet etching and conventional reactive sputtering, for the first time. It is experimentally found that static noise margin (SNM)at read condition increases with increasing s-ratio due to the strength of pull-down transistor. To overcome SRAM cell size increment with increasing s, a fin-height controlled pass-gate (PG) SRAM structure is proposed.

As one of promising metal gate materials, PVD TiN has widely been studied for conventional bulk-planar CMOS devices due to its high purity [1, 2]. However, there have been no systematical studies regarding the PVD TiN gate work function (tin) control using the nitrogen gas flow ratio (Rfrac12 = N2/(Ar+N2)) in the sputtering. In this paper, we present the Rfrac12 controlled tunable work function PVD TiN gate technology and its application for FinFET CMOS.

The impact of work function variation (WFV) in a metal gate (MG) electrode on low-frequency noise (LFN) is revealed for fin field-effect transistors (FinFETs). The LFN level is compared between the FinFETs having polycrystalline TiN and amorphous TaSiN MGs. The amorphous TaSiN MG exhibits a marked suppression of flicker noise in comparison with the TiN MG. The difference in the LFN level is correlated with the threshold voltage variability reflecting the WFV of the MG. By modeling the WFV of the TiN MG in the FinFET structure by three-dimensional device simulation, we clearly reveal the mechanism of the LFN increase by the WFV.

As advanced FinFET technologies, we have developed the co-integration techniques of the TiN gated high-performance 3T- and flexible V/sub th/ 4T-FinFETs. By using the conventional reactive sputtering of TiN, the well symmetrical V/sub th/ N- and P-channel 3T-FinFETs and the high V/sub th/-controllable 4T-FinFETs using the resist etch-back process have been demonstrated. The developed technologies are attractive to materialize the high-performance and power-managed FinFET CMOS circuits.

We have successfully developed the advanced FinFET fabrication processes for materializing FinFET CMOS circuits. Using the developed technologies, we demonstrate the advanced TiN metal gate, fin-height controlled FinFET CMOS inverter with an excellent transfer performance, and the flexible threshold voltage, asymmetric gate insulator thickness four-terminal (4T) FinFET with a greatly improved subthreshold (S) slope, for the first time.

The quantitative comparison of the electron mobility (u/sub eff/) in the poly-Si gated n-channel multi-FinFETs fabricated by the orientation-dependent wet etching and conventional RIB processes has been carried out. A remarkable increment in u/sub eff/ has experimentally been confirmed in the Si-fin channels fabricated by the wet etching instead of the RIB. Therefore, it is concluded that the developed wet etching technique is very attractive for the fabrication process of the high quality and ultra-thin Si-fin channel FinFETs.

Double-gate (DG) MOSFET structures have been regarded as promising candidates for scalable CMOS devices. Among DG concept devices, a vertical type has attracted considerable attention due to its process compatibility with conventional CMOS technology and its suitability with bulk Si substrates. The critical issue is fabrication technology, especially for the ultra-thin Si wall for the vertical transistor. This paper demonstrates, for the first time, vertical DG MOSFETs ('IMOSFETs') with a 15-nm-thick channel wall fabricated by using the newly-discovered ion-bombardment-retarded etching (IBRE) of Si in a tetramethylammonium hydroxide (TMAH) solution.

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (V t) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal–oxide–nitride–oxide–silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si–oxide–nitride–oxide–silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial V t roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (L g) is scaled down to 46 nm or less.

Influence of work function variation (WFV) in metal gates (MGs) on fluctuation of sub-threshold drain current is investigated in detail by analyzing fluctuation of current–onset voltage (COV) for fin field-effect transistors (FinFETs) with polycrystalline TiN and amorphous TaSiN MGs. The polycrystalline TiN MG exhibits anomalously increased COV fluctuation of the nMOS FinFETs in comparison to the pMOS case, while the amorphous MG exhibits well suppressed COV fluctuation both for the n- and pMOS FinFETs. Through the discussion with regard to the WFV due to the polycrystalline TiN grains, it is concluded that the sub-dominant grains of TiN with lower work function (WF) in TiN form localized potential valleys in the channel of the nMOS FinFETs resulting in the anomalous leak current in the sub-threshold condition. In the pMOS FinFETs, in contrast, the lower WF grains in TiN form localized potential peaks for holes, which have less impact on the sub-threshold leakage.

An amorphous TaSiN metal gate (MG) is introduced into double-gate fin field-effect transistors (FinFETs) to suppress work function variation (WFV) of the MG, which is a dominant source of threshold voltage (Vt) variability for MG FinFETs. Comparing with a poly-crystalline TiN gate, the TaSiN gate reduces Vt variation dramatically and thus records the smallest AVt value of 1.34 mV μm reported so far for the MG-FinFETs. By decomposing the variation source due to interface trap density, the WFV suppression using the amorphous MG is confirmed to be effective to achieve the well-suppressed variability of the MG-FinFETs.

In this study, we successfully introduced an atomic-layer-deposited (ALD) titanium nitride (TiN) gate grown with a tetrakis(dimethylamino)titanium (TDMAT) precursor into fin-type metal–oxide–semiconductor field-effect transistor (FinFET) fabrication for the first time, and comparatively investigated the electrical characteristics, including mobility and threshold voltage (V th) variation, of the fabricated ALD and physical-vapor-deposited (PVD)-TiN gate FinFETs. The ALD-TiN gate FinFETs showed superior conformality to the PVD-TiN gate FinFETs. The electron mobilities of the ALD- and PVD-TiN gate FinFETs were comparable in the small L g region. It was also confirmed that the ALD-TiN gate FinFETs showed a smaller V th variation than the PVD-TiN gate FinFETs.

The nanoscale wet etching of physical-vapor-deposited (PVD) titanium nitride (TiN) and its application to sub-30-nm-gate-length fin-type double-gate metal–oxide–semiconductor field-effect transistor (FinFET) fabrication are systematically investigated. It is experimentally found that PVD-TiN side-etching depth can be controlled to be one-half of PVD-TiN thickness with precise time control using an ammonium hydroxide (NH4OH) : hydrogen peroxide (H2O2) : deionized water (H2O) = 1 : 2 : 5 solution at 60 °C. Using the developed nanoscale PVD-TiN wet etching technique, sub-30-nm-physical-gate-length FinFETs, 100-nm-tall fin-channel complementary MOS (CMOS) inverters and static random access memory (SRAM) half-cells have successfully been fabricated and demonstrated. These experimental results indicate that the developed nanoscale PVD-TiN wet etching technique is very useful for tall fin-channel CMOS fabrication.

The low-energy tilted ion implantation (I/I) for fin-type double-gate metal–oxide–semiconductor field-effect transistor (FinFET) source–drain (SD) extension doping is systematically investigated experimentally by fabricating a series of n+-polycrystalline silicon (poly-Si) gate n-channel FinFETs under different I/I conditions. The on-state current (I ON) versus off-state current (I OFF) and the SD parasitic resistance (R p) are used for benchmarking the performance of the fabricated devices to investigate the optimal extension I/I conditions, including dose (D) and tilted angle (θ), at a fixed low energy of 5 keV. It is experimentally found that the best extension I/I conditions are D = 4×1014 cm-2 and θ= 60°. With further increasing D, the device performance deteriorates owing to the incomplete recrystallization of amorphous regions in the thin extension regions. In the case of θ= 0°, marked increment and fluctuations in R p are observed because the implant atoms scatter out randomly from each extension region. The R p value of the FinFETs fabricated under the above best I/I conditions is comparable to that of devices fabricated by the solid-phase diffusion of phosphors from phosphosilicate glass (PSG). This indicates that the extension I/I conditions of D = 4×1014 cm-2 and θ= 60° are almost optimal and is very effective for high-performance FinFET fabrication.

In this paper, we describe the superiority of the titanium nitride (TiN) film formed by atomic layer deposition (ALD) using a tetrakis(dimethylamino)titanium (TDMAT) precursor for metal-gate electrodes of planar metal–oxide–semiconductor field-effect transistors (MOSFETs). It was demonstrated that the resistivity of the ALD TiN was significantly reduced by NH3 post deposition annealing (PDA). The electrical characteristics of the ALD-TiN-gate MOS capacitors and planar MOSFETs were evaluated and compared with those of the physical-vapor-deposited (PVD) TiN. The performance of the ALD-TiN-gate cases was confirmed to be superior to that of the PVD-TiN-gate cases, which was explained by the lower interface trap density (D it) of the ALD TiN/SiO2 gate stack.

Sputtered titanium nitride (TiN) metal gates fabricated at different nitrogen gas flow ratios [RN=N2/(N2+Ar)] from 17 to 100% have systematically been investigated, and the RN dependence on the electrical characteristics of fabricated TiN metal gate bulk planar metal–oxide–semiconductor field-effect transistors (MOSFETs) and fin-type MOSFETs (FinFETs) are clarified. It is experimentally found that the electrical characteristics of FinFETs such as subthreshold slope (S-slope) and mobility are almost independent of RN, while those of bulk planar MOSFETs markedly deteriorate with increasing RN. These experimental results are discussed from the viewpoint of the device structure differences and the direction of energetic nitrogen atoms in sputtering. The threshold voltage (Vth) of FinFETs can be adjusted to about 100 mV by controlling RN without device performance degradation. These results are very useful in setting an appropriate Vth for TiN gate-last FinFETs.

The dependence of short-channel effects (SCEs) on the cross-sectional channel shape of the fin-type double-gate metal oxide semiconductor field-effect transistors (MOSFETs) has been experimentally investigated from the viewpoint of fin fabrication. The three types of fin-type double-gate MOSFETs (FinFETs) with a rectangular-cross-section channel on a (110)-oriented silicon-on-insulator (SOI) wafer, and a triangular and trapezoidal channels on a (100)-oriented SOI wafer were fabricated using the same orientation-dependent wet etching process. The experimental results show that the SCEs in rectangular-cross-section silicon (Si)-fin channel devices are well suppressed compared with those in a triangular or a trapezoidal Si-fin channel device fabricated using a similar mask pattern, in the regimes of the gate length of less than 85 nm and Si fin height of larger than 65 nm. The presented experimental results are valuable for FinFET design and fabrication.

Recently, a damage-free and highly efficient neutral-beam etching (NBE) system has been proposed using neutralization of negative ions generated in a pulse-time-modulated inductively coupled plasma (ICP) [Samukawa, 2002]. In this study, to find a potential solution for a damage free Si-Fin etching we demonstrated the new etching characteristics using the NBE. Rectangular Si-Fin channel and Si-FinFETs were successfully fabricated to take advantage of the low-energy and damage-free characteristic of the newly proposed neutral beam etching system.

The 3D fin-channel SONOS, MONOS and MANOS type flash memories with different gate and blocking layer materials have been successfully fabricated and their electrical characteristics have been comparatively investigated. It was found that MANOS type flash memory with an Al2O3 blocking layer and a TiN metal gate shows the better performance as compared to the SONOS and MONOS type ones thanks to the high-k effect of Al2O3 and the high gate work function of TiN.

The Ta/Mo interdiffusion gate technology was introduced into the gate-first FinFET process. The Ta/Mo gated n-MOS and the Mo gated p-MOS FinFET exhibited symmetrical Vth (0.31/-0.36 V), and the scalability down to 100 nm was demonstrated.