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The undoped 4-stacked Ge0.9Sn0.1 nanosheets sandwiched by double Ge0.95Sn0.05 caps without parasitic Ge channels underneath are realized by a radical-based highly selective isotropic dry etching. Highly inter-channel uniformity of the stacked GeSn nanosheets is realized by thin Ge0.9Sn0.1 (5 nm) channels and thick Ge0.95Sn0.05 caps to achieve high $\mathrm{I}_{\mathrm{\scriptscriptstyle ON}}$ . The caps are the barriers to separate the holes from the dielectrics/cap interface to reduce the surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( $ cm $^{-{3}}$ ) and heavily doped ( $\sim {2} \times {10}^{{21}}$ cm $^{-{3}}$ ) Ge at S/D can suppress the impurity scattering to increase the channel mobility and can reduce the S/D resistance, respectively. The high ${I}_{{\mathrm{\scriptscriptstyle ON}}} = {73}\,\,\mu \text{A}$ per stack (86 $\mu \text{A}/\mu \text{m}$ , normalized by the total perimeter of nanosheets) at ${V}_{\text {OV}} = {V}_{\text {DS}} = - {0.5}$ V is achieved for the device with the sheet width of 80 nm and the Lg of 80 nm. The quantum mechanical simulation shows that there is heavy hole population at the two ends of nanosheets.

The low contact resistivity with the median value of $3.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ (the lowest value of $1.1\times 10^{-{9}}\,\,\Omega \cdot \text {cm}^{{2}}$ ) is achieved by Ti metal contact to in-situ B-doped GeSn with B segregation at Ti/GeSn:B interface. The newly developed two-sheet-resistance model is used to extract the contact resistivity, considering the different sheet resistance of GeSn:B in the gap regions and under the metal layers. Sn incorporation into Ge lowers the Schottky barrier height of holes, and the heavy B doping at the Ti/GeSn:B interface reduces the hole tunneling distance. Fully compressively strained GeSn:B epitaxial layer with the bulk active [B] of $1.9\times 10^{{20}}$ cm−3 and [Sn] of 4.7% on the Ge-buffered Si substrate is successfully grown by chemical vapor deposition. The effects of B2H6 precursor on growth rate and [Sn] are investigated. Low contact resistivity is obtained using conventional B-doping in GeSn grown at a temperature as low as 305 °C and submitted to a post epitaxy thermal budget of 400 °C for 30 s.

The distinct photoresponse of the floating channels and the parasitic channels can be a signature to check the existence of the parasitic channel. The photoresponse of the sole parasitic channel mainly shows the photocurrent ( ${I}_{\text {ph}}$ ), while the photoresponse of the sole floating channels without parasitic channel shows the negative threshold voltage shift ( $\Delta {V}_{\text {T}}$ ) for nFET. The device with both the floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure.

The undoped 4-stacked Ge 0.9 Sn 0.1 nanosheets sandwiched by double Ge 0.95 Sn 0.05 caps without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. High inter-channel uniformity of the stacked GeSn nanosheets is achieved to enhance ION by thin Ge 0.9 Sn 0.1 (5nm) channels. The carriers are separated from dielectrics by the caps to reduce the impurity and surface roughness scattering. The double caps with small strain also stabilize the channels to prevent the channel buckling. The undoped GeSn nanosheets with [B] below the detection limit ( ON =73μA per stack (910μA/μm per channel footprint) at V OV =V DS =-0.5V is achieved among GeSn 3D FETs for the sheet width/Lg of 80nm/80nm. The I ON per channel footprint can be improved to 1070μA/μm with the sheet width scaled to 57nm due to the large carrier population at the two ends of nanosheets. The double caps as barriers for the holes in the Ge 0.9 Sn 0.1 nanosheets decrease the low frequency noise by reducing trapping/detrapping between the GeSn nanosheets and the gate dielectrics.

To detect the existence of the parasitic channel of GAAFET for the advanced technology nodes, a non-destructively optical method is investigated. With the infrared illumination at the wavelength of 1310 nm, 1550 nm, and 2000 nm, the main infrared responses of the stacked Ge 0.91 Sn 0.09 channels and the parasitic Ge 0.94 Si 0.06 channel are ΔV T and I ph , respectively. In addition, the photoresponses between the floating channels with the parasitic channel underneath and the transistors with the sole parasitic channel distinct from each other were observed. By distinguishing the optical responses under infrared illumination, the existence of the parasitic channel can be checked non-destructively.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89m V /dec and $\mathrm{I}_{\mathrm{O}\mathrm{N}}=42\mu 1$ per stack ( $10.5\mu A$ . per sheet) at $\mathrm{V}_{\mathrm{OV}}\mathrm{V}_{\mathrm{DS}}=-0.5\mathrm{V}$ are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H202 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.

The record low contact resistivity $(\rho_{\mathrm{c}})$ of Ti contact to Ge:B $(8.1\mathrm{x}10^{-10}\Omega-\mathrm{cm}^{2})$ is achieved by in-situ doped CVD using the high-order Ge precursor $(\mathrm{Ge}_{2}\mathrm{H}_{6})$ . The best achievable $[\mathrm{B}]_{\mathrm{act}}$ . of $7\mathrm{x}10^{20}\mathrm{cm}^{-3}$ and extended epitaxial process window are obtained using $\mathrm{Ge}_{2}\mathrm{H}_{6}$ . By optimizing the [B] and [Sn], 2% Sn addition into Ge epitaxy reaches the lowest $\mathrm{p}_{\mathrm{c}}$ of $4.1\mathrm{x}10^{-10} \Omega-\mathrm{cm}^{2}$ . Further Sn addition (4.7% and 13.2%) increases $\rho_{\mathrm{c}}$ due to reduced [B], and degrades the thermal stability. The record low resistivity $(2\mathrm{x}10^{-4}\Omega-\mathrm{cm})$ among epitaxial p-type Ge and GeSn is also demonstrated. Optimized metal etching processes ( $\mathrm{Cl}_{2}+\mathrm{BCl}_{3}$ for metal on $\mathrm{GeSn}:\mathrm{B}$ , while $\mathrm{C}1_{2}$ for metal on Ge:B) are necessary to minimize etching of GeSn:B and Ge:B, and to fabricate the test structure. A two-sheet-resistance model is used to correctly extract the $\rho_{\mathrm{c}}$ . B segregation $(> 1\mathrm{x}10^{21}\mathrm{cm}^{-3})$ at the metal/semiconductor interface enables the record low $\rho_{\mathrm{c}}$ .

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

Although the Sn content in GeSn can reach 10% using chemical vapor deposition, the reduction of Sn content by in-situ boron doping and solid phase doping by chemical vapor deposition are observed. The Sn loss increases with the increasing boron concentration in GeSn:B alloys, while there is no Sn reduction at the similar phosphorus doping level in GeSn:P. Based on the first principle calculations, the energy for boron to place Sn in GeSn is lower than that for boron to place Ge, indicating that boron atoms prefer to occupy Sn sites. The Sn loss is more serious for boron-implanted GeSn with thermal annealing at 400 °C than in-situ boron-doped GeSn even with 500 °C thermal annealing.

Although the melting laser annealing can activate the heavily phosphorus-doped epitaxial Ge on silicon-on-insulator by chemical vapor deposition, the dopant segregation occurs after the rapid thermal process at 550 °C for 3 min even with SiO2 capping. However, the active dopant concentration can be recovered after the second laser annealing to melt Ge again due to higher P solubility in the liquid Ge than the solid Ge. The temperature distribution and the melt depth of epi-Ge is mainly determined by the laser fluence. Selective laser annealing is used to simultaneously reach low dopant concentration in the channel regions for good gate controllability, and high concentration in the source and drain regions with low parasitic resistance for the transistors. As a result, the low specific contact resistivity of $1.2\ \times \,\,10^{-8}\,\,\Omega $ cm2 using the Ni–Ge/n+Ge, the 21% current enhancement of the Ge + Si nFET as compared to the device without the selectively second laser annealing and the Ni–Ge contact, and the similar subthreshold slope after the selectively second laser annealing are achieved. The Si channel underneath the Ge channel also contributes about 38% of the total current.

The aim of this work is to provide a systematic and comparative study on the material characteristics and electrical contact performance for a germanium-tin (GeSn) alloy with a high percentage of Sn (8%). Thin metal films (10 nm) of Nickel (Ni), Titanium (Ti), or Platinum (Pt) were deposited on Ge 0.92 Sn 0.08 layers and subsequently annealed at different temperatures ranging from 300°C up to 500°C. Various experimental techniques were employed to characterize the metal morphology and the electrical contact behavior, with the intention of identifying the most promising metal candidate, in terms of low sheet resistance and low surface roughness, considering a low formation temperature. The investigations carried out show that for nano-electronic contact applications, nickel-stanogermanide (NiGeSn) turns out to be the most promising candidate among the three different metals analyzed. NiGeSn presents low sheet resistance combined with low formation temperatures, below 400°C; PtGeSn shows better thermal stability when compared to the other two options while, Ti was found to be unreactive below 500°C, resulting in incomplete TiGeSn formation.

The phosphorus incorporation by chemical vapor deposition and activation by laser annealing reaches the electron concentration of $\sim 3\times 10^{20}$ cm $^{-3}$ . The pulsed laser not only activates the phosphorus but also produces the biaxial tensile strain of 0.35%. With the nickel germanide contact, the specific contact resistivity reaches as low as $1.5\times 10^{-8}~\Omega $ -cm2 by greatly reducing the tunneling distance. Due to 4% misfit between Ge and Si, there are still misfit dislocations near the Ge/Si interface. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with ON/OFF ratio of $\sim 1\times 10^{5}$ .

In this article we provide a comparative and systematic study on contact formation for germanium-tin (GeSn) thin films containing a high percentage of Sn (8 at.%). 20 nm of Nickel (Ni), Titanium (Ti), or Platinum (Pt) was deposited on Ge0.92Sn0.08 layers grown on Ge substrates, and subsequently annealed between 300 and 500 °C to form stanogermanide alloys. Several experimental techniques were employed to characterize the material and the electrical contact behaviour, with the purpose of identifying the most promising stanogermanide contact candidate, in terms of low sheet resistance, low surface roughness and low formation temperature. Among these three different metals we found that, for nanoelectronic applications, nickel-stanogermanide (NiGeSn) was the most promising candidate based on a low sheet resistance combined with a low formation temperature, below 400 °C. PtGeSn showed better behaviour in terms of thermal stability compared with the other two options, while Ti was found to be relatively unreactive under these annealing conditions, resulting in poor TiGeSn formation. For the lowest resistance stanogermanide contact generated, namely NiGeSn formed at 300 °C, detailed lattice resolution Transmission Electron Microscopy imaging, combined with fast Fourier transformation analysis, identified the formation of the Nix-1(GeSn)y-1 phase.

The electron concentration of 3×1020 cm−3 in phosphorus-doped Ge is obtained by in-situ chemical vapor deposition doping and laser annealing. The laser annealing effectively improve the crystallinity in the Ge layer. The pulse laser not only activates the phosphorus, but also produces the biaxial tensile strain. With the nickel germanide contact, the contact resistivity is as low as 1.5×10−8 Ω-cm2 by greatly reducing the tunneling distance. The misfit dislocations at the Ge/Si interface lead to the ideality factor of 1.6 for the Ge/Si hetero-junction diode with on/off ratio of ∼1×105.