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Among other new device concepts, nickel silicide (NiSix)-based Schottky barrier nanowire transistors are projected to supplement down-scaling of the complementary metal-oxide-semiconductor (CMOS) technology as its physical limits are reached. Control over the NiSix phase and its intrusions into the nanowire are essential for superior performance and down-scaling of these devices. Several works have shown control over the phase, but control over the intrusion lengths has remained a challenge. To overcome this, we report a novel millisecond-range flash-lamp-annealing (FLA)-based silicidation process. Nanowires are fabricated on silicon-on-insulator substrates using a top-down approach. Subsequently, Ni silicidation experiments are carried out using FLA. It is demonstrated that this silicidation process gives unprecedented control over the silicide intrusions. Scanning electron microscopy and high-resolution transmission electron microscopy are performed for structural characterization of the silicide. FLA temperatures are estimated with the help of simulations.

Here, we report the observation of negative photoconductance (NPC) effect in highly arsenic-doped germanium nanowires (Ge NWs) for the infrared light. NPC was studied by light-assisted Kelvin probe force microscopy, which shows the depletion of carriers in n-Ge NWs in the presence of infrared light. The trapping of photocarriers leads to high recombination of carriers in the presence of light, which is dominant in the n-type devices. Furthermore, a carrier trapping model was used to investigate the trapping and detrapping phenomena and it was observed that the NPC in n-Ge occurred, because of the fast trapping of mobile charge carriers by interfacial states. The performance of n-type devices was compared with p-type NW detectors, which shows the conventional positive photoconductive behavior with high gain of 104. The observed results can be used to study the application of Ge NWs for various optoelectronic applications involving light tunable memory device applications.

The fabrication of p-type silicon junctionless tri-gate transistors and their temperature dependent transport studies are reported in this work. The fabricated transistors have shown a good transfer characteristic down to a low temperature of ~ 80 K with an ON/OFF ratio of 106. The threshold voltage and the subthreshold slope were found to be dependent on temperature. In particular, the threshold voltage and the flat band voltage have positive slopes of 2.24 and 1.19 mV K−1, respectively, with temperature. Channel resistance was found to be increasing with decreasing temperature. The devices have shown a typical 1/f noise behavior in the frequency range of (1–50) Hz and 1/f2 type behavior in the frequency range of (50–100 Hz). At a temperature of 4.2 K, current vs. gate voltage characteristic at a fixed source drain bias shows clear coulomb peaks with different intervals for different gate bias voltages and the observed spikes were consistent within the sub-bands. We relate this to the single hole tunneling, mediated by the charged acceptors available in the channel region. Coupling strength of the dopants was also studied.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

A laboratory measurement of the α -decay half-life of 190 Pt has been performed using a low background Frisch grid ionisation chamber. A total amount of 216.60(17) mg of natural platinum has been measured for 75.9 days. The resulting half-life is ( 4.97 ± 0.16 ) × 10 11 years , with a total uncertainty of 3.2%. This number is in good agreement with the half-life obtained using the geological comparison method.

Films of self assembled diblock copolymers (BCPs) have attracted significant attention for generating semiconductor nanoarrays of sizes below 100 nm through a simple low cost approach for device fabrication. A challenging abstract is controlling microdomain orientation and ordering dictated by complex interplay of surface energies, polymer–solvent interactions and domain spacing. In context, microphase separated poly (styrene-b-ethylene oxide) (PS-b-PEO) thin films is illustrated to fabricate nanopatterns on silicon and germanium materials trenches. The trenched templates was produced by simple electron beam lithography using hydrogen silsesquioxane (HSQ) resist. The orientation of PEO, minority cylinder forming block, was controlled by controlling trench width and varying solvent annealing parameters viz. temperature, time etc. A noticeable difference in microdomain orientation was observed for Si and Ge trenches processed under same conditions. The Ge trenches promoted horizontal orientations compared to Si due to difference in surface properties without any prior surface treatments. This methodology allows to create Ge nanopatterns for device fabrication since native oxides on Ge often induce patterning challenges. Subsequently, a selective metal inclusion method was used to form hardmask nanoarrays to pattern transfer into those substrates through dry etching. The hardmask allows to create good fidelity, low line edge roughness (LER) materials nanopatterns.

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10(20) atoms cm(-3). Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.

The directed self-assembly of block copolymer (BCP) materials in topographically patterned substrates (i.e., graphoepitaxy) is a potential methodology for the continued scaling of nanoelectronic device technologies. In this Communication, an unusual feature size variation in BCP nanodomains under confi nement with graphoepitaxially aligned cylinder-forming poly(styrene)- block -poly(4-vinylpyridine) (PS- b -P4VP) BCP is reported. Graphoepitaxy of PS- b -P4VP BCP line patterns (C II ) is accomplished via topography in hydrogen silsequioxane (HSQ) modifi ed substrates and solvent vapor annealing (SVA). Interestingly, reduced domain sizes in features close to the HSQ guiding features are observed. The feature size reduction is evident after inclusion of alumina into the P4VP domains followed by pattern transfer to the silicon substrate. It is suggested that this nanodomain size perturbation is due to solvent swelling effects during SVA. It is proposed that using a commensurability value close to the solvent vapor annealed periodicity will alleviate this issue leading to uniform nanofi ns.

'Directing' block copolymer (BCP) patterns is a possible option for future semiconductor device patterning, but pattern transfer of BCP masks is somewhat hindered by the inherently low etch contrast between blocks. Here, we demonstrate a 'fab' friendly methodology for forming well-registered and aligned silicon (Si) nanofins following pattern transfer of robust metal oxide nanowire masks through the directed self-assembly (DSA) of BCPs. A cylindrical forming poly(styrene)-block-poly(4-vinyl-pyridine) (PS-b-P4VP) BCP was employed producing 'fingerprint' line patterns over macroscopic areas following solvent vapor annealing treatment. The directed assembly of PS-b-P4VP line patterns was enabled by electron-beam lithographically defined hydrogen silsequioxane (HSQ) gratings. We developed metal oxide nanowire features using PS-b-P4VP structures which facilitated high quality pattern transfer to the underlying Si substrate. This work highlights the precision at which long range ordered [similar]10 nm Si nanofin features with 32 nm pitch can be defined using a cylindrical BCP system for nanolithography application. The results show promise for future nanocircuitry fabrication to access sub-16 nm critical dimensions using cylindrical systems as surface interfaces are easier to tailor than lamellar systems. Additionally, the work helps to demonstrate the extension of these methods to a 'high [small chi]' BCP beyond the size limitations of the more well-studied PS-b-poly(methyl methylacrylate) (PS-b-PMMA) system.

The junctionless nanowire metal–oxide–semiconductor field-effect transistor (JNT) has recently been proposed as an alternative device for sub-20-nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS-compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain-induced-barrier lowering (DIBL) of 87 mV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

High-mobility materials and non-traditional device architectures are of key interest in the semiconductor industry because of the need to achieve higher computing speed and low power consumption. In this article, we present an integrated approach using directed self-assembly (DSA) of block copolymers (BCPs) to form aligned line-space features through graphoepitaxy on germanium on insulator (GeOI) substrates. Ge is an example of a high mobility material (III–V, II–VI) where the chemical activity of the surface and its composition sensitivity to etch processing offers considerable challenges in fabrication compared to silicon (Si). We believe the methods described here afford an opportunity to develop ultrasmall dimension patterns from these important high-mobility materials. High-quality metal oxide enhanced pattern transfer to Ge is demonstrated for the realization of nanofins with sub-10 nm feature size. Graphoepitaxial alignment of a poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) BCP was achieved using predefined hydrogen silsesquioxane (HSQ) topography at a GeOI substrate. Subsequent impregnation of the aligned BCP templates with a salt precursor in situ and simple processing was used to generate robust metal oxide nanowire (e.g., Fe3O4, γ-Al2O3, and HfO2) hardmask arrays. Optimized plasma based dry etching of the oxide modified substrate allowed the formation of high aspect ratio Ge nanofin features within the HSQ topographical structure. We believe the methodology developed has significant potential for high-resolution device patterning of high mobility semiconductors. We envision that the aligned Ge nanofin arrays prepared here via graphoepitaxy might have application as a replacement channel material for complementary metal–oxide–semiconductor (CMOS) devices and integrated circuit (IC) technology. Furthermore, the low capital required to produce Ge nanostructures with DSA technology may be an attractive route to address technological and economic challenges facing the nanoelectronic and semiconductor industry.

Supercritical resist drying allows the fabrication of high aspect-ratio (AR) resist patterns. The potential of this drying technique to increase the maximum achievable AR and the resolution of the overall lithographic process is analyzed for hydrogen silsesquioxane (HSQ). The maximum achievable AR is doubled compared to conventional nitrogen blow drying. Furthermore, the resolution is improved significantly.

Reactive ion etch (RIE) processes with HBr/O"2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12nm gate length and optimized photonic devices with ultrahigh Q-factors.

The surface roughness of hydrogen silsesquioxane (HSQ) as a negative tone electron beam (EB) resist has been studied as a function of exposure dose, developer concentration, and pre-exposure bake temperature. In the range of low exposure doses, the surface roughness of HSQ drops rapidly with an increase in the dose. It levels off at about 1 nm around the dose at which the respective contrast curve saturates. The TMAH developer concentration, varied in the range of 2.5–25%, has only a slight influence on the HSQ roughness. The increase of the baking temperature from 90 to 220 °C, however, causes a significant rise in the roughness of more than 100%. These results are discussed in terms of structural changes and network formation in thin HSQ films. They prove that a process combining high developer concentration and low baking temperature is preferable for fabrication of high resolution patterns using HSQ as a negative tone EB resist.

3D vertically stacked silicon nanowire (SiNW) field effect transistors (FET) with high density arrays (up to 7×20) of fully depleted and ultra-thin (15–30 nm) suspended channels were fabricated by a top-down CMOS compatible process on silicon on insulator (SOI). The channels can be wrapped by conformal high-κ gate dielectrics (HfO 2 ) and their conductivity can be excellently controlled either by a reference electrode or by three local gates; a backgate (BG) and two symmetrical Pt side-gates (SG) offering unique sensitivity tuning. Such 3D structure has been (3-Aminopropyl)-triethoxysilane (APTES) functionalized and biotynilated for pH and streptavidin (protein) sensing, respectively. An ultra-low concentration of 17 aM of streptavidin was measured, the lowest ever reported in literature. Extremely high quasi-exponential drain current responses (ΔI d /pH) of ∼0.70 dec/pH were measured for structures with APTES functionalized SiO 2 gate dielectrics when operated in the subthreshold regime. Also, high drain current responses > 20 µA/pH and high sensitivities (S ∼ 95%) were measured for structures with a native oxide gate dielectrics when operated in the strong-inversion regime.

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high I on /I off current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.

A 3D, vertically stacked silicon nanowire (SiNW) field effect transistor (FET) featuring a high density array (7×20) of fully depleted channels has been successfully fabricated by a CMOS compatible process on silicon on insulator (SOI) and functionalized for streptavidin detection for the first time. The channels are surrounded by conformal high-κ gate dielectrics (HfO2), and their conductivity can be uniquely tuned by three gates; a backgate (BG) and two symmetrical Pt side gates (SG) through a liquid, offering unique sensitivity tuning with high gate coupling (SS=75 mV/dec, α'=SS60mV/dec/SSmeasured=0.8, with highest sensitivity=93-99%, obtained for I=1 0pA-10nA, in weak inversion) ever published.

Germanium is a promising high-mobility channel material for future nanoelectronic devices. Hydrogen silsesquioxane (HSQ) is a well known high-resolution electron beam lithography (EBL) resist, which is usually developed in aqueous based developers. However, this feature of HSQ causes troubles while patterning Ge surface as it is always shielded with native Ge oxides. GeO2 is a water soluble oxide, and since HSQ resist is developed in aqueous solvents, this oxide interferes with the patterning. After the EBL exposure, GeO2 is washed off during the development, lifting the patterned structures and making the high-resolution patterning impossible. To avoid this issue, it is necessary to either clean and passivate the Ge surface or use buffer layers between the native Ge oxides and the HSQ layer. In this article, a novel technique to clean the Ge surface prior to HSQ deposition, using simple “household” acids like citric acid and acetic acid, is reported. The acids are able to remove the native Ge oxides as w...

A high-gain photodetector based on junctionless MOSEFT has been presented in this work. Tri-gate junctionless nanowire phototransistors were fabricated on (100) silicon-on-insulator wafers with a buried oxide of thickness 145 nm and top silicon layer of thickness 10 nm. The gate stack consisted of a 10 nm SiO2 dielectric and a 50 nm poly-Si gate electrode. The channel length and doping concentration of junctionless n-MOSFETs was 1 μm and 3 × 1019 cm−3, respectively. The dark current of this device measured at room temperature was less than 1 pA. The measured internal gain of the device was about 35 for 860 nm light illumination. The photocurrent was 300 times larger than the dark current for only 30 nW incident power on the nanowire at 300 mV drain bias.

A single step metal assisted etching (MAE) process, utilizing metal ion-containing HF solutions in the absence of an external oxidant, has been developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. Detailed characterisation of both the porous and non-porous sections of the Si nanowires was provided by transmission electron microscopy studies, enabling the mechanism of nanowire roughening to be ascertained. The versatility of the MAE method for producing heterostructured Si nanowires with varied and controllable textures is discussed in detail.

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.

An initial top-down process of Germanium nanowires is developed in this work. The Silicon Nitride (Si 3 N 4 ) is used as a hard mask to obtain a stable surface for lithography and a resistive mask for etch. The electron-beam lithography (EBL) is utilized for patterning the nanowires with Hydrogen Silsesquixane (HSQ) as a negative photoresist. Several different etch conditions are examined to transfer the patterns into the substrate.

Study of topographical and structural changes occurring in a positive resist known as SML after electron beam lithography are presented in this article. The authors also defined its chemical structure, which is very important for understanding the lithographic performance of the resist. The structural and lithographic properties of SML have been compared to the traditional ZEP resist. First, the change in the surface roughness with respect to the electron dose of SML and ZEP resists was measured. It was found that both resists start off with similar initial roughness values. However, ZEP was observed to have a higher roughness at the apex electron dose, thereafter a reduction in roughness was observed. The roughness variation in the two resists reflected on the resolution of the gratings that were patterned in both the resists. Gratings in SML showed smoother line edge roughness, and the patterns transferred using SML resist showed more even features than the ones transferred with ZEP. Subsequently, to understand the chemical composition of the new resist, Fourier transform infrared spectroscopy (FTIR) measurements were performed on both the resists as well as on poly(methyl methacrylate) (PMMA) and their spectra were compared. The FTIR spectra revealed that SML had a chemical structure similar to ZEP and PMMA polymers. The high sensitivity of ZEP is attributed to the Cl group in the compound, which is not present in SML and PMMA and can therefore explain their lower sensitivity to electron exposure in comparison to ZEP. Unlike PMMA but comparable to ZEP, SML shows an IR peak at a wavenumber close to 850 cm−1, suggesting the presence of α-methylstyrene group within its chemical structure, which accounts for the resist's high etch durability, similar to ZEP. Additional FTIR measurements of pre- and postexposed resists together with their attributions to the resolution of the SML and ZEP resists is also demonstrated in this article. The data presented in the study highlights the chemical properties of SML and ZEP resists polymers and correlates them to their lithographic performance.

Surface roughness (SR) and, especially, the closely related line-edge roughness (LER) of nanostructures are important issues in advanced lithography. In this study, the origin of surface roughness ...

The effect of high frequency (1MHz) acoustic agitation (megasonic agitation) on development of electron beam exposed poly(methylmethacrylate) (PMMA) nanostructures is investigated. Test patterns consisting of dense holes, isolated lines, and gratings with high aspect ratios have been used. Compared to conventional dip development, the sensitivity of the development process is increased and the homogeneity of nanopatterns is improved considerably. Furthermore, experiments towards ultimate aspect ratios and resolution of PMMA in the range of 2–3nm with megasonically assisted development have been carried out. The physical mechanisms for the observed enhanced development performance which is particularly attractive for nanostructuring are discussed.

An extensive study of parameters pertinent to electron beam lithography with hydrogen silsesquioxane as a negative tone electron beam resist is presented. With higher developer concentrations contrast and reproducibility are improved significantly at the expense of lower sensitivity. In a similar way extended delays between the baking and exposure degrade the sensitivity but increase the contrast. In contrast, at higher baking temperatures the sensitivity is improved but the contrast and reproducibility deteriorate. These results are discussed within a microscopic model. Contrast values as high as 10 and good reproducibility have been obtained with a developer concentration of 25% tetramethyl ammonium hydroxide and a baking temperature of 90 °C. With these optimal parameters an experimental lithographic pattern of 50 nm lines and spaces could be resolved in 220 nm thick HSQ resist film exposed at 50 keV.

Electrically variable shallow junction metal–oxide–semiconductor field effect transistors on silicon on insulator have been fabricated to evaluate the suitability of fabrication processes on a nanoscale. In addition, the limits of scalability have been explored reducing gate lengths down to 12 nm. Specific attention has been paid to the overlay accuracy as required for the fabrication of these double gate structures. The superior quality of hydrogen silsesquioxane (HSQ) as electron beam resist and as mask material is demonstrated. The transistor fabricated exhibits extremely low leakage currents and relatively high on currents. The 8 orders of magnitude difference between the on and off states demonstrates conclusively large potentials for metal–oxide–semiconductor structures with critical dimensions in the 10 nm regime.

Silicon nanowire (Si NW) sensors have attracted great attention due to their ability to provide fast, low-cost, label-free, real-time detection of chemical and biological species. Usually configured as field effect transistors (FETs), they have already demonstrated remarkable sensitivity with high selectivity (through appropriate functionalisation) towards a large number of analytes in both liquid and gas phases. Despite these excellent results, Si NW FET sensors have not yet been successfully employed to detect single molecules of either a chemical or biological target species. Here we show that sensors based on silicon junctionless nanowire transistors (JNTs), the simplest possible transistors, are capable of detecting the protein streptavidin at a concentration as low as 580 zM closely approaching the single molecule level. This ultrahigh detection sensitivity is due to the intrinsic advantages of junctionless devices over conventional FETs. Apart from their superior functionality, JNTs are much easier to fabricate by standard microelectronic processes than transistors containing p–n junctions. The ability of JNT sensors to detect ultra-low concentrations (in the zeptomolar range) of target species, and their potential for low-cost mass production, will permit their deployment in numerous environments, including life sciences, biotechnology, medicine, pharmacology, product safety, environmental monitoring and security.