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Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured $\sim 120~\Omega /\mu \text{m}$ for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5 nm node. This paper demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. The characteristics of CMOS in close proximity to floating BPR are found to be similar to the characteristics of CMOS without BPR. Moreover, W-BPR interface with Ru via contact can withstand more than 320 h of electromigration (EM) stress at 4 MA/cm 2 and 330°C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

This paper demonstrates high performance strained p-type double stacked Ge Gate-AlI-Around (GAA) devices at significantly reduced gate lengths $(\text{L}_{\text{G}}\sim 25\text{nm})$ compared to our previous work. Excellent electrostatic control is maintained down to $\text{L}_{\text{G}}=25$ nm by using extension-less scheme, while the performance is kept by appropriate spacer scaling and implementation of highly B-doped Ge or GeSn as source/drain (S/D) material.

A tri-layered in situ grown RuTiN barrier system for advanced interconnects was developed using plasma-enhanced atomic layer deposition (PE-ALD) from tetrakis(dimethylamino)titanium, (pyrrolyl-methylcyclopentadienyl)ruthenium and N2/H2 plasma. The system consists of an ultrathin TiN nucleation layer to enable Ru growth on Si oxide substrates, a bulk RuTiN layer, and a top Ru film to ensure compatibility with Cu and electrochemical Cu deposition techniques. It is shown that the nucleation layer does not need to be continuous and that 0.6–0.7 nm is sufficient to enable Ru nucleation on oxides. Layer closure studies of a Ru cap grown on RuTiN films indicate that the minimal thickness to have a closed Ru layer at the top surface is around 1.0 nm. 3 nm RuTiN films show good oxidation resistance and Cu barrier properties for interconnect applications when compared to the well-known TaN barrier system. Furthermore, conformal deposition in narrow lines has been obtained. As such, we demonstrate that using the flexibility of the PE-ALD process, composition controllability of the bulk and interfaces can be achieved for sub 3 nm thin RuTiN barriers. The interface composition can be optimized for compatibility with bottom and top layers, which makes the system a viable candidate for future interconnect technologies.

Cu wire resistance reduction using CVD Mn-based Self-Formed Barrier (SFB) compared to conventional PVD barrier was investigated at 40 and 100nm half pitch (HP). Mn-based SFB leads to both (1) maximum fractional Cu area in the trenches and (2) Cu resistivity reduction at scaled dimensions. This represents a breakthrough for future interconnect scaling. Blanket Cu experiments suggest that the Cu resistivity reduction in the case of Mn-based SFB can be attributed to lower surface scattering at the dielectric/Cu interface. Finally, promising reliability has been demonstrated in 20nm HP single damascene (SD) SiO 2 trenches integrated with Mn-based SFB.

We investigate void nucleation and growth during electromigration in 30 nm half pitch Cu lines. Diffusion interfaces are varied a) by using SiCN dielectric cap or a CoWP metal cap and b) by tuning the thickness of TaN/Ta barrier metal. The developed local sense EM test method and in-situ EM observations allow understanding void nucleation and growth stages. For the SiCN cap, independent of barrier thickness, there are two void growth modes sensitive to grain structure. In contrast, for the CoWP cap, a single mode independent of the grain structure is observed, where a nucleated void is pinned in the test line. We also show that Co diffuses into the interface between the barrier metal and Cu, and suppresses Cu diffusivity at that interface. As both Cu diffusivities at the cap and barrier interfaces are suppressed by the presence of Co, a CoWP cap is beneficial to electromigration for advanced interconnects where thinner barrier metals are required.

Electromigration failure times of 100 nm wide dual damascene Cu interconnects have been evaluated over a very wide range of different stages of void formation and growth. Voids that did not span the whole line width and height have been monitored using the so-called local sense structures, while standard single via structures were used to study fully grown voids. The activation energy E a did not change over the whole experimental range of failure times indicating that the main diffusion path during void formation and growth does not change in our semi-bamboo lines. The earlier reported increase in distributional spread σ after full void formation is less pronounced during void formation which is due to different kinetics before and after full void formation. The use of defining failure criteria before full void formation has been explored as a tool to reduce electromigration test times. Due to the constant E a , test times can be reduced by over a factor of two.

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

In this paper we report on the successful integration of a 90nm low-k full VIA-first dual damascene process architecture using carbon-doped-oxide (CDO) and SiC etch-stop-layer (ESL). One of the key features of the integration scheme is that the effects of photoresist poisoning have been eliminated by optimization of the low-k (k < 3.0) film stack deposition process. The mechanisms underlying photoresist poisoning have been investigated through detailed partition studies. Electrical yield and reliability data will be shown to demonstrate the performance of the overall integration approach.