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We discuss advances in our research on 300mm GaN NMOS by demonstrating GaN-on-Si(111) NMOS transistors achieving low R ON =330Ω-μm; high ID,max=1.7mA/μm; BV DS (at I D =1μA/μm) of up to 90V with excellent R ON =660Ω-μm; record f T /f MAX of 200/350GHz for GaN-on-Si; industry’s best RF switch R on C off =55fs; and highest mmwave (28GHz) RF power amplifier peak PAE of 65% @ 19.5dBm saturated power. We discuss and compare the challenges in approaches to GaN and Si CMOS integration research including: (a) poly-silicon CMOS, (b) heterogeneous epitaxy of GaN and Si(111) CMOS, (c) wafer-to-wafer bonding [2], and (d) 3D monolithic Si(100) layer transfer using bonding techniques [1],[3].

Tunneling Field Effect Transistor (TFET) has attracted interest due to its steep-SS prospects [1]. Although a number of sub-60mV/dec TFETs were demonstrated [2], many failed to realize this feat due to non-optimized geometry, material choice [3], and material defects [4, 5]. In this paper, we clearly distinguish the requirement for i) geometry, ii) semiconductor BTBT characteristics, iii) semiconductor defects and iv) oxide interface defects. Using Ge as a case study, multi-temperature characterization of experimental PIN diodes is used to separate bulk properties from the interface effects, calibrating the models for BTBT, trap-assisted-tunneling (TAT) and SRH. The measured BTBT characteristic of a material is as important as the effect of defects; even a zero-defect TFET using the calibrated Ge material requires thin body and thin oxide. Bulk SRH and TAT is found to be a less critical issue for thin body TFETs, whereas interface defect density ∼1012cm−2 is low enough to only degrade TFET SS

A comprehensive quantum anisotropic transport model for holes was used to study silicon PMOS inversion layer transport under arbitrary stress. The anisotropic band structures of bulk silicon and silicon under field confinement as a twodimensional quantum gas are computed using the pseudopotential method and a six-band stress-dependent k.p Hamiltonian. Anisotropic scattering is included in the momentum-dependent scattering rate calculation. Mobility is obtained from the Kubo-Greenwood formula at low lateral field and from the fullband Monte Carlo simulation at high lateral field. Using these methods, a comprehensive study has been performed for both uniaxial and biaxial stresses. The results are compared with device bending data and piezoresistance data for uniaxial stress, and device data from strained Si channel on relaxed SiGe substrate devices for biaxial tensile stress. All comparisons show a very good agreement with simulation. It is found that the hole band structure is dominated by 12 "wings," where mechanical stress, as well as the vertical field under certain stress conditions, can alter the energies of the few lowest hole subbands, changing the transport effective mass, density-of-states, and scattering rates, and thus affecting the mobility

This paper summarizes the electrostatics and performance of III–V field effect transistors including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs (TFETs). The electrostatics of the III–V devices is shown to improve from thick body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET structures, sub-threshold slope (SS) steeper than 60 mV/decade has been demonstrated in III–V TFETs. These III–V devices, especially the 3-D tri-gate MOSFET and TFET, are viable options for future ultra low power applications.

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (I D ) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase I D by more than 20X.

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5A with low J G , and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar T OXE , the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

In this paper for the first time, the logic performance of Schottky-gate In 0.7 Ga 0.3 As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V eff ) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V eff enables 65% intrinsic drive current gain at V CC = 0.5V and 20% gain at V CC = 1.0V for the In 0.7 Ga 0.3 As QWFET over that of Strained Si, despite 2.5x lower charge density.

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

The onset of localized conduction in TaOx- and TiOx-based resistive switching devices during forming has been characterized. The novel temperature and voltage dependencies of forming times were extracted with pulsed forming experiments that spanned five orders of magnitude in time and showed three different regimes of electroforming. A universal field-induced-nucleation theory which included self-heating effects was used to explain a strong reduction in forming voltage with increasing forming time over all observed regimes of electroforming. It was shown that the effective activation energy for the incubation time changes inversely proportional with the electric field. A diameter of the volatile filament that precedes forming was estimated at ∼1 nm.

The electronic and vibrational properties of carbon nanoribbons (CNRs) are analyzed and compared to carbon nanotubes (CNTs). Transport properties are analyzed from the perspective of use in an FET device. The required sizing and consequent processing requirements are discussed. The overall properties of the CNRs and CNTs are found to be similar, with the primary difference being the more restrictive size vs. bandgap behavior of the CNRs.

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

The hole surface roughness and phonon limited mobility in the silicon 〈100〉, 〈110〉, and 〈111〉 square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high 〈110〉 and 〈111〉 valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in 〈100〉 and 〈110〉 wires. The 〈111〉 channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence...

Electronic properties of graphene (carbon) nanoribbons are studied and compared to those of carbon nanotubes. The nanoribbons are found to have qualitatively similar electron band structure which depends on chirality but with a significantly narrower band gap. The low- and high-field mobilities of the nanoribbons are evaluated and found to be higher than those of carbon nanotubes for the same unit cell but lower at matched band gap or carrier concentration. Due to the inverse relationship between mobility and band gap, it is concluded that graphene nanoribbons operated as field-effect transistors must have band gaps