Search

We present a silicon nitride (SixNy) arrayed waveguide grating (AWG). Crosstalk in this AWG was reduced by decreasing the phase error in a multimode arrayed waveguide (WG) at center wavelength of 838 nm. 8-channel SixNy AWGs using arrayed WGs with double-etched inverse-tapered WG structure and cross-sectional area of $1.5 \times 1.5\,\,\mu \text{m}^{{2}}$ were fabricated. The AWG exhibited less than −29.6-dB crosstalk with 0.43-dB insertion loss for transverse electric (TE) polarization.

We investigated silicon nitride(SixNy) arrayed waveguide grating (AWG) with multimode arrayed waveguide at 850nm wavelength to reduce phase error due to the sidewall roughness of the waveguide. The fabricated 8-channel SixNy AWG shows low crosstalk of -30dB and low loss of 0.5dB.

We present cost effective $2 \times 2$ silicon nitride Mach-Zehnder interferometric thermo-optic switches with 1 mm-length phase shifter. Devices were fabricated on a bulk silicon wafer with CMOS compatible process. The footprint was ~0.7 mm2. For the device designed for $\lambda \!\!\sim 1310$ nm, we demonstrated ~26.8-dB crosstalk, 0.23-dB insertion loss, and 17.25- $\mu \text{s}$ switching speed at $\lambda \!\!\sim 1325.8$ nm. Similarly, $\lambda \!\!\sim 1550$ nm device showed the ~24.7-dB crosstalk, 0.48-dB insertion loss, and 17.48- $\mu \text{s}$ switching speed at $\lambda \!\!\sim 1550.8$ nm. The measured operating power was 55.6 and 64.4 mW at $\lambda \!\!\sim 1325.8$ nm and $\lambda \!\!\sim $ 1550.8 nm, respectively.

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Advancement of silicon photonics technology can offer a new dimension in data communications with un-precedent bandwidth. Increasing the integration level in the silicon photonics is required to develop compact high-performance chip-level optical interconnects for future systems. Especially, monolithic integration of light source on a silicon wafer is important for future silicon photonic integrated circuits, since realizing a compact on-chip light source on a silicon wafer is a serious issue which impedes practical implementation of the silicon photonic interconnects. At present, due to the lack of a practical light source based on Group IV elements, flip chip-bonded or packaged lasers based on III–V semiconductor are usually being used as external light sources, to feed silicon modulators on SOI wafers to complete a photonic transmitter, except the reported silicon hybrid lasers monolithic-integrated on SOI wafers. To overcome above problem, we have proposed a compact on-chip light source, the directly monolithic-integrated VCSEL on a bulk silicon wafer (VCSEL-on-Si), based on the transplanted epitaxial film by substrate lift-off process and following device-fabrication on the bulk Si wafer. This can offer practical low-power-consumption light sources integrated on a silicon wafer, which can provide a complete chip-level I/O set when combined with monolithic-integrated vertical-illumination Ge-on-Si photodetectors on the same silicon wafer. In this work, we report the characterization of direct-modulation VCSELs-on-Si for λ ~850 nm with CW optical output power > ~2 mW and the threshold current < ~3 mA, over 10 Gb/s operations. We also discuss about the thermal characteristics of the VCSELs-on-Si.

Based on either a SOI wafer or a bulk-silicon wafer, we discuss silicon photonic devices and integrations for chip-level optical interconnects. We present the low-voltage silicon PICs on a SOI wafer, where Si modulators and Ge-on-Si photodetectors are monolithically-integrated for intra-chip or inter-chip interconnects over 40 Gb/s. For future chip-level integration, the 50 Gb/s small-sized depletion-type MZ modulator with the vertically-dipped PN-depletion-junction (VDJ) is also presented. We report vertical-illumination-type Ge photodetectors on bulk-silicon wafers, with high performances up to 50 Gb/s. We present the bulk-silicon platform for practical implementation of chip-level interconnects, and the performance of the photonic transceiver silicon chip.

We investigate the improvement of an insertion loss in silicon arrayed waveguide grating (AWG), by analyzing the multimode generation due to the field-mismatching effect. 8 channel silicon AWGs on a 6” SOI wafer are fabricated with an ultra-shallow etching structure and various aperture size of arrayed WGs. Our experimental results demonstrate the improved insertion loss and crosstalk characteristics. The fabricated AWG shows an insertion loss less than 1 dB with a crosstalk of -23.2 ~ -25.6 dB, exhibiting ~2.5 dB improvement of insertion loss and ~5 dB improvement of crosstalk, compared to our reported result.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube and LAN, SAN, data center and network applications.

Zn 1 x Mn x Te epilayers have been grown on GaAs (1 0 0) substrates by hot-wall epitaxy. The structure of the epilayers was found to be zincblende over the whole range of the composition. The lattice parameters and the compositions were determined with double crystal rocking curves. Exciton-related near-edge emissions were observed in the 10 K photoluminescence spectrum without an external magnetic field. The peak energy of the edge emission increased linearly with increasing Mn composition up to 60%. The intra-ion transition emissions were observed in high Mn composition epilayers and the transition energy did not depend on the Mn composition.

We investigate the single-mode operation in a silicon arrayed multi-mode waveguide grating. By introducing a double-etched structure at the boundary of a star coupler with inverse-tapered waveguides (WGs), the suppression of the mode-coupling between adjacent arrayed multi-mode WGs, and the adiabatic optical mode conversion between a FPR (free propagation region) and arrayed WGs can be achieved with a reduced phase error of the arrayed WGs. The fabricated four-channel Si arrayed waveguide grating (AWG) demonstrates a good performance level, such as a low insertion loss of 0.61 dB (0.73 dB) and low adjacent crosstalk less than −31.3 dB (−32.2 dB) for transverse-electric (TE) (transverse-magnetic, TM) polarization, in the range of ~1300 nm wavelength.

This paper reports a fiber-to-chip coupler consisting of a silicon inverted taper and a silicon oxynitride (SiON) double stage taper, where the cascaded taper structure enables adiabatic mode transfer between a submicron silicon waveguide and a single mode fiber. The coupler, fabricated by a simplified process, demonstrates an average coupling loss of 3.6 and 4.2 dB for TM and TE polarizations, respectively, with a misalignment tolerance of +/- 2.2 mu m for 1 dB loss penalty. (C)2013 Optical Society of America

We present a silicon-on-insulator Echelle grating 8-channel demutiplexer showing characteristic features, average insertion loss 2.4 dB measured at 1520 similar to 1570 nm, adjacent channel crosstalk 15-18 dB, and channel spacing 11.9 nm. Our Echelle grating is remarked by a total internal reflector (TIR) which reflects incident light by a single reflection in contrast to the double reflections of retro-reflector TIR Echelle gratings. (C) 2012 Optical Society of America

We have studied gain dynamics of InAs/InGaAsP quantum dot semiconductor optical amplifier. The recovery time at the ground state was ~3 ps, much faster than the previously reported values at 1.5 um.

The photoluminescence efficiency and carrier recombination time of p-type modulation doped InAs/GaAs quantum dots (QDs) have been measured as a function of doping density. At 10 K the carrier lifetime decreases from 1200 to 350 ps over the doping range of 0 and 30 acceptors/QD. This behavior is attributed to an enhancement of the Auger-type recombination due to the presence of extrinsic holes in the QDs. The hole density dependence of the Auger process is found to be weaker than in bulk semiconductors and quantum wells (QWs). (c) 2008 American Institute of Physics.

We investigate the reduction of transition loss across the star coupler boundary in a silicon arrayed waveguide grating (AWG) by suppressing multimode generation and scattering near the boundary of a star coupler. Eight-channel silicon AWGs were designed with optimal conditions based on enhanced field matching in combination with ultrashallow etched structures. The fabricated AWG demonstrates an insertion loss down to 0.63 dB with a cross talk of -23 to -25.3 dB, exhibiting ~0.8 dB improvement of insertion loss and ~4 dB improvement of cross talk compared to the Si AWG fabricated with a conventional double-etch technique.

The gain and phase dynamics of a high quality quantum dot semiconductor optical amplifier were measured at various wavelengths. In the ground state (GS), the amplitude of the slow component was negligible and the fast dominant gain recovery time was 0.7 ps. In the excited state (ES), the slow component was not negligible although small. The time required to recover from 90% to 10% was 2.0 ps in the GS but gradually increased to 31 ps in the ES. This finding predicts no pattern effects in the GS, but finite pattern effects in the ES.

Selective area growth was adopted to grow high-quality quantum dots (QDs) of different energy levels on the same plane at 1.5 μm. At room temperature, the photoluminescence (PL) peak of InAs/InGaAsP QDs on InP substrate was shifted from 1445 to 1570 nm for sample 1 (from 1385 to 1485 nm for sample 2) in a plane, with a PL intensity comparable to those of regular samples grown without dielectric patterns. The dot shape was a round dome, with the density reduced by 28% and the height increased by 17%. Time-resolved PL indicated that the selectively grown QDs behaved similarly to regular QDs. These results open up a practical method for in-plane integration of QD devices.

Modulation-doped InAs/GaAs quantum dots (QDs) show bright photoluminescence (PL) at 300 K, linear increase of PL intensity on excitation at 300 K and rather temperature insensitive PL intensity and carrier lifetime, in contrast to undoped QDs. Systematic analyses indicate that those advantageous behaviors come from the enhanced Coulomb attraction due to excess carriers in doped QDs. The stronger Coulomb interaction increases the thermal activation energy, keeps more carriers in QDs, and provides enhanced QD characteristics at room temperature.

Carrier lifetimes have been measured for long-wavelength emitting InAs quantum dots (QDs) capped with a thin GaAsSb layer. Above a critical Sb composition, a type-II system is formed, resulting in an increase in the carrier lifetime. The carrier lifetime in a strongly type-II structure is increased by a factor ∼54 in comparison to the lifetime in a type-I structure. In addition, the type-II carrier lifetime varies across the inhomogeneously broadened ground-state emission, while the type-I QD lifetime is invariant.