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A self-aligned sacrificial emitter (SASE) process has been successfully developed in a BiCMOS technology. Selective epitaxy of SiGe originally developed for sub-100 nm CMOS nodes is used for a raised extrinsic base. Process integration includes building a sacrificial emitter pedestal using a CMOS gate-like etch, isolation of the emitter to extrinsic base by oxide CMP, and oxide recess etch to expose the emitter window for the in-situ doped emitter. Electrical results are shown to be comparable to hardware manufactured using other BiCMOS integration schemes. An intriguing growth mode of selective epitaxy has been found to have higher growth rate for high index planes.

Peak f T of 660GHz is reported for HBT f T doubler designs in IBM 90nm SiGe BiCMOS technology 9HP. This high performance f T doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and f T is also investigated. f T doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBM's large volume 200mm fabrication line. The technology features 300 GHz f T and 360 GHz f MAX high performance SiGe HBTs, 135 GHz f T and 2.5V BV CEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.

In this paper, we discuss a novel technique to reduce base resistance (R b ) and collector-base capacitance (C cb ) for higher F max in high-speed SiGe HBTs. In order to reduce C cb , we first located the origins of the different components of C cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C cb , namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R b by reducing the base link resistance.