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As transistor technologies continue to scale and device density increases, junction formation requirements are subject to increasing challenges. Ion implantation is the preferred approach for junction formation due to its precise control of dopant depth and dose. These aspects are crucial to deliver finely tuned transistor performance and limit device variation. Arsenic and phosphorus (n-type) dopants are used at many process steps to dope crystalline silicon, polycrystalline silicon, or other substrates in advanced memory devices. Arsenic, due to its heavy mass, will readily amorphize crystalline silicon, particularly at high dose rates. Conventional thermal processing is used to recover crystalline silicon amorphization, but may be subject to residual defects. Heating the substrate during implantation is a novel technique, which has been adopted in advanced semiconductor devices to limit the amorphous region and allow for complete recrystallization in subsequent thermal processes [1]. This work demonstrates wafer-level results of heating the substrate in a plasma doping (PLAD) tool.

This work demonstrates that the sequence of a Ge co-implant with a B 2 H 6 PLAD in the source/drain is very critical in order to improve advanced PMOS performance. Locating the Ge co-implant after the B 2 H 6 PLAD resulted in higher total retained B dose and less implant damage. PMOS performance was significantly improved compared to B 2 H 6 PLAD without the Ge co-implant or Ge co-implant before B 2 H 6 PLAD. The Ge implant energy was optimized to locate the Ge peak around the B deposition layer/Si substrate interface for a better knocking effect and less implant damage. With the optimized Ge implant conditions the source/drain contact resistance and sheet resistance were significantly reduced, while the junction leakage current was not degraded. As a result, PMOS I ds improved by 12%, transconductance KL improved by 14%, and I OFF variation improved by 33% without significant change in mean I OFF . This process helps overcome technical challenges of B 2 H 6 PLAD, providing a path for continued scaling of PMOS junction depth with improved device performance.

The demand for low resistance metallization solutions has become an increasingly important issue as interconnect line sizes have approached and in some cases become smaller than the electron mean free path in Cu. Formation of reliable small damascene Cu features with high aspect ratio pose major challenges to void free Cu fill process development. Surfaces and interfaces now begin to play a more dominant role in scaled interconnects, with critical defect sizes becoming much smaller than before. Interfacial engineering between copper and liner/seed, liner/seed to barrier, as well as critical defect control from galvanic corrosion and CuOx nodule formation are also key components of successful metallization development. In this paper, we discuss some critical copper process challenges, focusing on copper barrier/liner, seed, fill, heat treatment, CMP and clean processes development to attain low resistance and reliable metallization.

SiF4 PLAD has been systematically characterized and optimized. The correlations between the etching, deposition, retained F dose and profile as functions of the PLAD process variables including implant voltage, RF power, pressure, pulse duty cycle, and the diluting gases have been extensively investigated. It was found that PLAD process by using pure SiF4 is in an etching or RIE regime, but can be adjusted to minimize the etching effect. It was found that diluting SiF4 with different gases can significantly impact etching and deposition characteristics. The selectivity of etching and deposition behaviors on the different substrate materials such as poly-Si, silicon oxide, and silicon nitride have been explored. With the understanding of these behaviors, SiF4 PLAD can be optimized for multiple precision doping and material modification applications.

The continuous anodic oxidation technique/differential Hall effect technique is used to study damage engineering of ultralow energy doping. It has been found that the scattering defect concentrations of the beam-line (BL) implants strongly correlate to the implant ion specie atomic mass unit and energy. Plasma doping (PLAD) seems to show a different mechanism for scatter defects. PLAD processes can have an in situ B-deposited film during implant and have less direct ion bombardment on the Si surface. The low scattering defect concentrations of PLAD implants (B2H6 and BF3) indicate that PLAD implants show an intrinsic advantage over BL counterparts in the current process regime.

New carrier drift mobility data for boron-, phosphorus-, and arsenic-doped Si in a low-energy high-dose implant regime are measured and studied using a continuous anodic oxidation technique/differential Hall effect technique. The data show that, when the doping concentration is >; 1020/cm3, both the hole and electron mobility values are lower than the conventional model predictions, and the electron mobility of the As-doped Si is lower than that of the P-doped ones. The data also show that, when the doping concentration is >; 1021/cm3 the hole mobility in the B-doped Si and the electron mobility in the P-doped Si are almost equal and reach as low as ~40 cm2/V · s, and the electron mobility of the As-doped Si is the lowest and reaches ~30 cm2/V · s. These mobility data are much lower than the conventional model predictions and are also lower than the previously published data. For the ULSI device and circuit analyses, simulations, and designs, these new mobility data need to be taken into consideration.

Combination of transmission electron microscopy and secondary ion mass spectrometry methods and device characteristics are used to successfully study damage engineering of the B-based low energy ion implants. The depths and densities of the amorphizing (a-Si) layer (surface lattice damage) and the end of range (EOR) damage are found to correlate to ion mass (amu) and implant energy, which are scalable to the molecular ion implants and ultralow energy) implants. The B11 beam-line implant shows thinner both a-Si and EOR depths due to its smaller amu and lower energy, and the damage are well annealed under the current annealing conditions. The BF2 beam-line implant shows severe surface lattice damage by more amorphizing due to its larger amu and higher energy, and needs more thermal budget to annealing (recrystallizing). The B2H6 plasma doping (PLAD) shows moderate a-Si layer and less EOR damage than beam-line ones which attributes to B deposition as a screen so that there are no direct ion bombardments on S...

Angle-resolved X-ray photoelectron spectroscopy method was used to study self-sputtering effects of different n-type low-energy doping techniques, including conventional monoatomic 75As and 31P beam-line ion implants and AsH3 plasma doping (PLAD). It has been found that the self-sputtering effects of the beam-line implants correlate with the mass of ion species. As beam-line implant shows more serious self-sputtering effect than monoatomic P and B beam-line implants. Very low energy P implants show surface-swelling phenomena. PLAD process using AsH3 gas species has no sputtering effects but has slight deposition under current process condition.

A new method and apparatus called Faraday/ion mass spectroscopy (IMS) dosimeter system is developed and can be used to determine the implanted impurity dose and profile for any molecular or multispecies-based plasma immersion ion implantation (PIII)/plasma doping (PLAD) processes. Good agreement between the boron doses measured by this method and those measured by SIMS has been demonstrated. Because of its direct, real-time, in situ, and close-loop control manner, this method shows a good controllability and repeatability for the PIII/PLAD processes.

The P+ plasma doping (PLAD) process using B 2 H 6 /H 2 plasma in a pulsed, RF-excited plasma system has been systematically characterized and optimized. The correlations between the deposition, retained B dose/profile, carrier dose/profile, sheet resistance ( R S ) as a function of the pulse voltage, nominal dose, and carrier gas dilution have been extensively investigated. It was found that diluting B 2 H 6 with H 2 can be used as a method to control and minimize boron deposition. SIMS and SRP analyses indicate that B and carrier profiles are deeper for higher dilutions up to 5/95 of a B 2 H 6 /H 2 gas ratio, than they are for lower dilutions due to less B deposition. This results in a higher activation fraction because of the B SS limit and compensates for the reduction of the retained B dose. The higher dilutions also improved the retained B dose and R S saturation due to less deposition. The PLAD process of a pulsed, RF-excited plasma system using B 2 H 6 diluted with 92.5% to 95% H 2 was found to be an optimal condition for high-dose, boron-doping applications.

We extensively investigate tool and recipe set-up dependence of the ultra-shallow junctions (USJ) doped by the boron-based ultra-low energy (ULE) beam-line (BL) implants. Recipes set-up includes different tools, energies, implant temperatures, and deceleration ratios. Channeling effect and energy contamination issues are de-coupled by drift and deceleration mode implants. A channeling effect factor (CEF) is defined and quantified. Channeling effect is found to be a major factor causing deeper profiles and long tails (x j ). Channeling effect gets worse when the implant energy is reduced due to less self-PAI effect (with less damage). Low temperature (−100 °C) implant does not effectively reduce channeling effect. Deceleration mode implant increases tail (x j ) due to energy contamination as a secondary order effect.

Plasma immersion ion implantation (PIII) technology is an alternative that overcomes the limitations of conventional beam line ion implantation for shallow, high dose and 3D doping on advanced memory and logic devices. This technique also delivers a better CoO as the result of higher productivity, smaller footprint and lower operating costs. With the requirements of new device architecture such as FINFET or FD-SOI for Logic, reduction of cell sizes for Memories, or 3D integration for “More than Moore” applications, a shallow profile is not the only critical objective. Amorphization and defects prevention become key points to allow good recrystallization and activation after annealing while reducing the thermal budget. IBS has developed and implemented the technique of high temperature implantation (up to 500°C) on the PIII system, PULSION®. In this paper, we present the impact of high temperature AsH3 Plasma doping in silicon. ARXPS (Angle Resolution X-ray Photoelectron Spectroscopy), SIMS (Secondary Ion Mass Spectrometry), and TEM (Transmission Electron Microscopy) analysis are used to study impact of the temperature on doping profiles and amorphization layer thickness. We show that when “high” acceleration voltage and high doses are used, thickness of the amorphization layer is drastically reduced (figure 1), and when lower acceleration voltage is used, amorphization layer can be totally suppressed.

Conventional beam-line (BL) implant shows a poor scalability of profiles (x j ) versus energy at the ULE implant regime due to serious channeling effect and energy contamination issue. B 2 H 6 PLAD shows intrinsic channeling effect immunity with a totally different mechanism. An in-situ, build-in B deposition layer is formed during PLAD process as a screen amorphous layer to minimize channeling effect and reduce the surface damage residues as well. For above reasons, B 2 H 6 PLAD shows a good scalability of profiles (x j ) versus energy, and achieves better R S -x j characteristics and x j abruptness, and then better device performance including lower series and contact resistances, better I ON /I OFF ratio and less short channel effect (SCE), etc. than BL implant counterparts.

Toppling during clean process is a general structure issue when we scale down critical dimension (CD)/increase aspect ratio (AR) and density of the nano structures. In this paper, we demonstrated a novel process with CH 4 PLAD (plasma doping) conformal process to eliminate the toppling issue. A uniform C deposition layer from CH 4 PLAD process wrapped the whole structure on the top/bottom/sidewall and made structure more robust during clean process. As a result, the toppling issue could be eliminated. The PLAD condition should be chosen in the “highly collisional case” in order to maximize deposition and minimize implant. ARXPS (angle resolved X-ray photoelectron spectroscopy) and PDP1 (plasma device planar 1D) simulation were applied to define the “highly collisional case”. There was a strong correlation between implant dose and toppling reduction rate. Besides CH 4 PLAD, other neutral species such as GeH 4 PLAD may also be used for this process. The advantages of this process include no thermal Dt, fast throughput and low cost. It may help us to continue scaling down the structures with higher AR/smaller CD/higher density.

This Poster Session discusses the following: PMOS Device Performance Improvement using Buried Contact Implants; Deep Trench Patterning and Lift-off Resist in Micro-fluidic Devices; and Nano-ionic Conductive Bridge Memristors based on Chalcogenide Glasses: Electrical Performance Characterization and Modeling.

Comparison study of doping a 3D trench transistor structure was carried out by beam-line (BL) implant and plasma doping (PLAD) methods. Electron holography (EH) was used as a powerful characterization method to study 2D cross-sectional doping profiles of boron-based doping processes. Quantitative definitions of junction depths xj in both vertical and lateral directions can be obtained. Good correlations of 2D electron holography dopant profiles, 2D dopant profile simulations, and 1D SIMS/ARXPS impurity profiles are demonstrated. The results reveal an advantage of PLAD over BL implant: a much larger effective implant area for 3D trench bottom. It leads to a larger lateral junction depth xj(L) with a comparable vertical junction depth xj(V). It is attributed to the PLAD technology with no line of sight shadowing effect and less angle variation issues. Enhancing the dopant lateral straggle by PLAD at the trench bottom is particularly useful for non-planar device structures with low resistance buried dopant layers.

The effects of self-amorphization thickness on boron (B) dopant depth profile in silicon (Si) were investigated by cold temperature implant, down to −100°C. Significant B junction depth (Xj) reduction can be achieved for as-implant and post anneal, when the self-amorphization thickness is comparable or deeper than the B implant projected range (implant peak position) and the implant is completed at sufficiently low temperature. There is a transition temperature regime before the appropriate temperature is reached. The Xj reduction is stagnated due to the thickness limitation and the degree of self-amorphization. Temperature dependent surface damage, self-amorphization thickness, diffusion, and activation were also studied. Improvement in carrier mobility is more significant in certain dose regimes at low temperatures. The findings of this study provide important insight in to the control of the junction profile for smaller atomic mass unit (AMU) species, like B, by using the self-amorphization effect at cold temperatures.

This work demonstrates that the sequence of a Ge co-implant with a B 2 H 6 PLAD in the source/drain is very critical in order to improve advanced PMOS performance. Locating the Ge co-implant after the B 2 H 6 PLAD resulted in higher total retained B dose and less implant damage. PMOS performance was significantly improved compared to B 2 H 6 PLAD without the Ge co-implant or Ge co-implant before B 2 H 6 PLAD. The Ge implant energy was optimized to locate the Ge peak around the B deposition layer/Si substrate interface for a better knocking effect and less implant damage. With the optimized Ge implant conditions the source/drain contact resistance and sheet resistance were significantly reduced, while the junction leakage current was not degraded. As a result, PMOS I ds improved by 12%, transconductance KL improved by 14%, and I OFF variation improved by 33% without significant change in mean I OFF . This process helps overcome technical challenges of B 2 H 6 PLAD, providing a path for continued scaling of PMOS junction depth with improved device performance.

Comparative As and P beamline implantations were subjected to a series of low, high, low, high anneals and evaluated after each step. Following high temperature anneals, there is an increase in carrier concentration, a decrease in mobility, and an increase in the concentration of mobility scattering defects.

BF2 beamline and B2H6 PLAD implants were evaluated after a series of low, high, low, high anneals. Following a high anneal, we find an increase in mobility and a decrease in concentration of mobility scattering defects.

The focus of this paper is a comparative study of the advanced boron-based ultra-low energy (ULE) doping techniques on ultra-shallow junction (USJ) fabrications, including beam-line atomic 11B implant, BF 2 , B 18 H 22 , C 2 B 10 H 12 molecular implants, cluster B implant, and B 2 H 6 and BF 3 PLAD implants. It has been found that B 2 H 6 PLAD and B 18 H 22 molecular implants demonstrate the best R S -x j and abruptness characteristics. Beam-line BF 2 implant shows poor R S -x j characteristics due to its serious RIE effect by F species. Cluster B implant shows the worst R S -x j characteristics and a very rough surface. Both are attributed to its serious self-sputtering effect because of its much larger and heavier ion species although further optimization may lead to improvement.

New carrier mobility (μ) data for boron-, phosphorus-, and arsenic-doped Si in a low-energy, high-dose implant regime are measured and studied using continuous anodic oxidation technique/differential Hall effect (CAOT/DHE) technique. The data show that when the doping concentration is >1020/cm3, both hole and electron mobility values are lower than the conventional model predictions, and the electron mobility of the As-doped Si is lower than the P-doped ones. The data also show that when the doping concentration is >1021/cm3, the hole mobility in B-doped Si and the electron mobility in P-doped Si are almost equal and reach as low as ~40 cm2/V sec, and the electron mobility of As-doped Si is the lowest and reaches ~30 cm2/V sec. These mobility data are much lower than the conventional model predictions and are also lower than the previously published data. For the ULSI device and circuit analyses, simulations, and designs, these new mobility data need to be taken into consideration.

At a given thickness of HfO 2 , atomic layer deposited (ALD) TaN metal-gates showed higher equivalent oxide thickness (EOT) and flat-band-voltage (V fb ) shift compared to physical vapor deposited (PVD) TaSiN after annealing at 750degC for 30 min in N 2 . TEM data revealed the growth of a thicker interfacial oxide of 1.7 nm for TaN compared to 0.9 nm for TaSiN. In addition, TaN showed higher effective workfunction of 4.7 eV compared to 4.4 eV for TaSiN. However, both TaN and TaSiN exhibited V fb roll-off when the HfO 2 thickness was decreased below 4 nm. XPS measurements showed the presence of 6 atom% oxygen in TaN, whereas no significant amount of oxygen was detected in TaSiN. Electrical results are discussed in terms of the oxygen content in metal-gates and oxygen vacancy in HfO 2 .

A newly‐developed surface analysis technique, which combines Secondary Ion Mass Spectrometry (SIMS) with Angle‐Resolved X‐ray Photoelectron Spectroscopy (ARXPS), was used to achieve more accurate results of the retained impurity doses and profiles for ultra‐low energy implants, including conventional beam‐line implant and plasma immersion ion implantation (PIII). Using this method, it has been found that the B2H6 (Diborane) PIII demonstrates thicker native oxide and much more B dose loss during RTP and surface clean treatments than conventional beam‐line ion implantation, due to the higher surface B concentration. In order to match the electrical parameters of the device, PIII must consider higher nominal dose to compensate the B loss.

A functional DRAM with higher data retention characteristics than a planar access device has been demonstrated, using a metal gate recessed access device (RAD). Chemical vapor deposition (CVD) and atomic layer deposition (ALD) were used to deposit titanium nitride (TiN) and tantalum nitride (TaN), respectively. CVD TiN and ALD TaN-CVD TiN laminate gate stacks were integrated with a RAD module. ALD TaN-CVD TiN laminate gates showed enhanced drive current (IDS), higher transconductance (GM), higher mobility (?EFF) and reduced off current (IOFF) characteristics compared to CVD TiN gates. Device characteristics and reliability data for both the planar devices and RADs are presented. The ALD TaN-CVD TiN laminate metal gate RAD showed much improved data retention characteristics compared to a conventional planar device with a poly silicon gate. The optimum thickness of ALD TaN in the laminate stack is discussed.

Thermally stable TiN and TaN-TiN laminate metal gates for PFETs are demonstrated using a conventional CMOS process flow with SiON gate dielectric. TaN-TiN laminate gates show enhanced drives (I/sub D/), higher transconductance (G/sub M/), higher mobility (/spl mu/ /sub EFF/, and reduced off current (I/sub OFF/) characteristics compared to TiN gates. The optimum thickness of TaN in the laminate stack is discussed. The as-deposited work function of the TaN-TiN laminate gate stack and TiN was found to be /spl sim/ 5.0eV.

The impacts of the native oxides and the impurity loss mechanisms of low energy doping process for both p-type and n-type implants have been quantitatively studied using secondary ion mass spectrometry/angle-resolved x-ray photoelectron spectroscopy method. The low energy doping processes include conventional beamline implant and plasma immersion ion implantation (PIII). It has been found that the native oxides play very significant roles on the low energy implants, especially for PIII due to its unique impurity profiles. The results show very different behaviors on p-type and n-type implants because of the SiO2∕Si interface segregation mechanisms. p-type (boron-based) doping loses more impurities into the native oxide, but n-type (arsenic-based) doping does not lose impurities. These results can be used to optimize the semiconductor processes such as implant, strip, clean, and thermal-annealing process.

A method called time-delayed, time-resolved Langmuir probe measurement is used to measure pulsed plasmas to overcome the secondary electron emission during high-voltage pulses. The plasma densities of the pulsed-mode plasma or any plasmas with secondary electron issues can be measured and analyzed by using this method.

It has been reported that helium dilution of B2H6 in the plasma doping (PLAD) process can be used to control and minimize deposition phenomenon. In this article we quantify the impact of such dilution on boron doping and deposition under PLAD conditions appropriate for ultrashallow junction formation. The sheet resistance (RS) of the implanted wafers remains nearly constant when B2H6 is diluted with He up to 95%, although the retained B dose is reduced. Secondary ion mass spectroscopy profiles indicate that B profiles are deeper for higher dilution than for lower dilution due to less B deposition. The deeper B profiles contribute to a higher activation fraction during annealing due to the B solid solubility limit. This higher activation compensates for the reduction of the retained B dose. The plasma doping process of a pulsed glow-discharge system by using B2H6 diluted with 95% provides optimal conditions for minimizing deposition. This results in a higher doping rate and then higher throughput.