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Abstract: The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of ‘pulsed power’. First results from a prototype device that approaches the pixel size of 20μm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18μm imaging CMOS process, instead of a conventional CCD process. [ABSTRACT FROM AUTHOR]

Abstract: The Linear Collider Flavour Identification (LCFI) Collaboration is developing the sensors, readout electronics and mechanical support structures for the vertex detector of the International Linear Collider (ILC). High speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below the 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs), Column Parallel Readout chips (CPRs) and Column Parallel Driver chips (CPDs) have been developed. The CPCCD has to operate at a clock frequency of 50MHz, which represents a difficult technical challenge due to the large sensor capacitance. The design and performance of the second generation CPCCD sensors, CPC2, and the new driver chip, CPD1, which meet these challenging requirements, are described. [ABSTRACT FROM AUTHOR]

Abstract: The LCFI Collaboration is developing the sensors, readout electronics and mechanical support structures for the Vertex Detector (VXD) of the International Linear Collider (ILC). High-speed readout is needed to ensure that the occupancy due to the pair production background at the ILC is kept below 1% level. In order to satisfy this requirement, Column Parallel CCDs (CPCCDs) and Column Parallel Readout chips (CPRs) have been developed. The CPCCD has to operate at a clock frequency of 50MHz, which represents a difficult technical challenge due to the relatively large sensor capacitance. The design and performance of planar transformers, which can be used to provide the required 20A clock current, are described. [Copyright &y& Elsevier]

Abstract: The Linear Collider Flavour Identification (LCFI) collaboration has successfully developed the first prototype of a novel particle detector, the In-situ Storage Image Sensor (ISIS). This device ideally suits the challenging requirements for the vertex detector at the future International Linear Collider (ILC), combining the charge storing capabilities of the Charge-Coupled Devices (CCD) with readout commonly used in CMOS imagers. The ISIS avoids the need for high-speed readout and offers low power operation combined with low noise, high immunity to electromagnetic interference and increased radiation hardness compared to typical CCDs. The ISIS is one of the most promising detector technologies for vertexing at the ILC. In this paper we describe the measurements on the charge-shielding properties of the p-well, which is used to protect the storage register from parasitic charge collection and is at the core of device''s operation. We show that the p-well can suppress the parasitic charge collection by almost two orders of magnitude, satisfying the requirements for the application. [Copyright &y& Elsevier]

Abstract: The In Situ Storage Image Sensor (ISIS) is a monolithic active pixel sensor with memory cells in each pixel. The memory cells are implemented as a CCD register. A test device with parameters suitable for tracking charged particles has been constructed and characterized. The characteristics of a proof-of-principle ISIS device are described and results from using the sensor as a tracking device for high energy electrons are presented. [Copyright &y& Elsevier]

Abstract: The in situ storage image sensor (ISIS) is a monolithic active pixel sensor with memory cells in each pixel. The memory cells are implemented as a CCD register. This and other features of the sensor make the ISIS an excellent device for detectors that will be used at the International linear collider (ILC), an electron-positron accelerator with a proposed centre-of-mass energy of around 500GeV. The sensor can be made very thin while retaining a high signal-to-noise ratio. The memory cells can be read out between bunch trains at a relatively low clock speed, hence limiting power consumption. The actual signal charge is stored in potential wells and not on capacitors, minimizing the sensitivity to electromagnetic interference. This paper presents the results of the first beam test of the first ISIS prototype. The measurements made include the signal-to-noise ratio, position resolution and efficiency. [Copyright &y& Elsevier]