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Dielectric breakdown mechanism of gate dielectrics has been reconsidered with SiO2 films of various thicknesses ranging from 3.6 to 9.5 nm. Careful time-dependent dielectric breakdown (TDDB) measurements have realized the detection of anomalous lifetime (TBD) lowering than the expectation from generally accepted power-law (PL) model at relatively low-voltage region in 6- and 6.5-nm-thick films. Analysis from the viewpoint of the hole and electron fluence to breakdown (QBD,hole and QBD,el) has demonstrated the dominant carrier change(DCC) from hole to electron with the lowering of the stress voltage. These results strongly support the DCC model. The DCC model provides stress voltage-independent defect generation efficiencies of electron and of hole at the stress voltage region where each carrier dominates the breakdown, while the PL model provides the stress voltage-dependent efficiency. The DCC model is also capable to explain the empirically reported linear electric field (E) dependence of TBD in a wide range of stress voltage which supports the thermochemical model (E-model). Therefore, it is expected that the DCC model can also be employed in the lifetime prediction of gate dielectrics thicker than ~5 nm, where the E-model is generally employed in the lifetime insurance of actual market products. The DCC model is expected to give longer predicted TDDB lifetimes at the actual device operating conditions in most devices than the E-model and other models and, hence, more aggressive usage of gate dielectric films can be realized. [ABSTRACT FROM AUTHOR]