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The BEOL Barrier-Seed deposition process is a key component in achieving the desired electrical and electro-migration performance while balancing the step coverage. The process also has a multifold impact on wafer yield parametric since it serves multiple passes for the various metal levels. Two major challenges with the barrier sputter deposition are: (A) achieving optimal within-feature barrier coverage while balancing resistance parameters; (B) flake defectivity — the process is prone to flake defectivity due to inherent adhesive properties of nitride films. Several different parameters play a role in dictating the quality and quantity of the barrier film that is being deposited. This paper analyzes the impact of one such critical parameter — the AC bias during barrier deposition to modulate the chamfer coverage and the electrical Via-resistance. Furthermore it elucidates the methodology of addressing the source of massive killer flakes that cause severe pattern damage that act as "killer" defects for the dies. Post implementation of the changes discussed, the massive defects of interest that were sourced from the sputter process were completely eliminated. A detailed study supported by electrical and cross-sectional analysis allowed zeroing in on the optimal Bias power to derive the best possible chamfer stability while being able to achieve a lower Via-resistance as desired.