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When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/ f2 phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor-limited quality factor and the capacitor-limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub-harmonic and super-harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub-harmonic voltage-controlled oscillator followed by an injection-locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1-MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 µm). [ABSTRACT FROM AUTHOR]