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The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

Single event upset (SEU) threatens the reliability of spaceborne integrated circuits (ICs). As the process of transistors continues to scale, Single-Node-Upset (SNU) and Double-Node-Upset (DNU) hardened circuits no longer meet the requirements of high reliability. A disadvantage of previous Triple-Node-Upset (TNU) hardened circuits is high overhead. Therefore, this paper proposes a fault-avoidance TNU-resilient latch (FATNU) using approximate C-elements (ACs) and new fault-avoidance C-elements (FACs). Simulation results demonstrate that FATNU achieves TNU resilience with low overhead compared with reference latches due to the use of the clock-gating technique and cross-feedback loop. In particular, compared with previous TNU-resilient latches, the FATNU latch is the best in delay, power, and area overhead. Moreover, the proposed FATNU latch is insensitive to process, voltage, and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4 × 4 array in four levels. The point is heterogeneous interconnection of each level. Compared with the traditional interconnection way, the proposed heterogeneous interconnection can block the propagation of TNU effectively. The IHTRL can effectively realize TNU recovery by the blocking ability of C-elements and heterogeneous interconnection. The IHTRL utilizes the high-speed path and clock-gating technique to reduce performance penalty and power consumption. Compared with TNU recovery latches LCTNURL and TNURL, the proposed IHTRL is the best in terms of delay, area overhead and PDP. Compared with TNU tolerant and recovery latches, the IHTRL achieves 81.96% reduction in delay on average, 85.91% reduction in PDP on average and 85.46% reduction in APDP on average, at the cost of 7.14% increase in power consumption and 13.21% increase in area overhead on average. Analysis shows that the IHTRL is insensitive to PVT variations. [ABSTRACT FROM AUTHOR]