1. Top gate engineering of field-effect transistors based on wafer-scale two-dimensional semiconductors
- Author
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Minxing Zhang, Lingyi Zong, Xinyu Wang, Wenzhong Bao, Xiaojiao Guo, Peng Zhou, Yin Wang, Yin Xia, Chen Luo, Chenjian Wu, Ling Tong, Jingyi Ma, Xinyu Chen, David Wei Zhang, Chuming Sheng, Saifei Gou, Xing Wu, and Yaochen Sheng
- Subjects
Materials science ,Polymers and Plastics ,business.industry ,Mechanical Engineering ,Transistor ,Metals and Alloys ,Hardware_PERFORMANCEANDRELIABILITY ,law.invention ,Threshold voltage ,Semiconductor ,Mechanics of Materials ,law ,Logic gate ,Hardware_INTEGRATEDCIRCUITS ,Materials Chemistry ,Ceramics and Composites ,Inverter ,Optoelectronics ,Field-effect transistor ,Wafer ,business ,Hardware_LOGICDESIGN ,Voltage - Abstract
The investigation of two-dimensional (2D) materials has advanced into practical device applications, such as cascaded logic stages. However, incompatible electrical properties and inappropriate logic levels remain enormous challenges. In this work, a doping-free strategy is investigated by top gated (TG) MoS2 field-effect transistors (FETs) using various metal gates (Au, Cu, Ag, and Al). These metals with different work functions provide a convenient tuning knob for controlling threshold voltage (Vth) for MoS2 FETs. For instance, the Al electrode can create an extra electron doping (n-doping) behavior in the MoS2 TG-FETs due to a dipole effect at the gate-dielectric interface. In this work, by achieving matched electrical properties for the load transistor and the driver transistor in an inverter circuit, we successfully demonstrate wafer-scale MoS2 inverter arrays with an optimized inverter switching threshold voltage (VM) of 1.5 V and a DC voltage gain of 27 at a supply voltage (VDD) of 3 V. This work offers a novel scheme for the fabrication of fully integrated multistage logic circuits based on wafer-scale MoS2 film.
- Published
- 2022