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In this work, for the first time, a study was conducted of the existence of Extraordinary Optical Transmission (EOT) in Silicon (Si) thin films with subwavelength holes array and high excess carrier concentration. Typically EOT is studied in opaque perforated metal films. Using Si would bring EOT and its many applications to the silicon photonics realm and the mid-IR range. Since Si thin film is a semi-transparent film in mid-IR, a generalization was proposed of the normalized transmission metric used in literature for EOT studies in opaque films. The plasma dispersion effect was introduced into the studied perforated Si film through either doping or carriers’ generation. Careful consideration for the differences in optical response modeling in both cases was given. Full-wave simulation and analysis showed an enhanced transmission when using Si with excess carriers, mimicking the enhancement reported in perforated metallic films. EOT was found in the mid-IR instead of the visible range which is the case in metallic films. The case of Si with generated excess carriers showed a mid-IR EOT peak reaching 157% around 6.68 µm, while the phosphorus-doped Si case showed a transmission enhancement of 152% around 8.6 µm. The effect of varying the holes’ dimensions and generated carriers’ concentration on the transmission was studied. The analogy of the relation between the fundamental mode cutoff and the EOT peak wavelength in the case of Si to the case of metal such as silver was studied and verified. The perforated Si thin film transmission sensitivity for a change in the refractive index of the holes and surroundings material was investigated. Also, a study of the device potential in sensing the hole and surroundings materials that have almost the same refractive index yet with different absorption fingerprints was performed as well.

Dielectrophoretic force has been used to manipulate and control the biological microparticles. This technique has been used for various purposes such the cell trapping, cell sorting and separating the different biological particles suspended in a buffer solution. The strength of dielectrophoretic force depends on different features related to the cell dielectric features and geometry of the electrodes. Label-free and non-invasive techniques are considered promising in the analysis of the cell. The impedance spectroscopy is matching with the advantages of these techniques. In this paper, we study the influence of the modification of the geometry of the electrodes as the source of dielectrophoresis force on impedance spectroscopy techniques. The main target is to enhance the sensitivity of the system to differentiate between the cells with allow conductivity.

This paper demonstrates the effect of microelectrodes configuration on the sensitivity and accuracy of the micro-electrical impedance spectroscopy (μEIS). Bi-polar and tri-polar microelectrodes configurations were presented, fabricated and experimentally used to extract the electrical parameters of Human Bone Osteosarcoma Epithelial (U2OS) viable and dead cells. A comparison between the experimental results are presented and discussed. These experimental results show that the tri-polar electrode configuration has higher sensitivity compared to bi-polar configuration. Keywords: Bio impedance, U2OS cells, μEIS, Microfluidic platform

The dielectrophoresis (DEP) is the motion of polarizable particles which is a result of the interaction between a non-uniform electric field and the induced dipole moment of these particles. The electro-kinetic DEP is a widely used technique for biological cells’ manipulation, characterization and separation. The electro-kinetic DEP consists of three major configurations, they are; traveling wave dielectrophoresis (twDEP), electro-rotation dielectrophoresis (rotDEP), and levitation (levDEP). In this paper, a design of electrokinetic platform that includes the three electrokinetic configurations is presented and discussed. The design of the electrokinetic platform is implemented and simulated using 130 nm complementary metal-oxide-semiconductor (CMOS) technology. Also, this paper presents a developed technique to design the electrokinetic platform's electrodes. This developed technique is the usage of SKILL scripting of cadence (SSC) language. CMOS is a technology which is used to fabricate integrated circuits (IC). SKILL is a scripting language which supports the automation of a specific layout design by commands. The layout of electrokinetic DEP platform is developed using SSC. The performance of the developed electrokinetic platform using SSC versus the platforms based on the other traditional techniques is presented and evaluated using COMSOL Multiphysics®.

In this work, we present the design of a refractive Axicon lens to be used in refractive index optical sensing. The lens is designed to generate a Bessel – Gauss beam at the wavelength of 3.3 microns. At that wavelength, the absorption of the CH4 is maximum and thus a maximum change in the refractive index due to the CH4 gas is also expected. The intensity profile of the generated beam is quite sensitive to the index of refraction of the surrounding medium. Placing the optical detector at the point of maximum change in the intensity with refractive index allows the measurement of the refractive index change and hence the gas percentage with very high sensitivity. Our design shows sensitivity greater than 970 % per RIU. We also develop an analytical formulation for the intensity variation with the refractive index. The results obtained analytically are confirmed by the finite difference time domain FDTD calculation. From the analysis and the derived expressions, we demonstrate the effect of the Axicon base angle on the sensitivity and hence allow for the lens optimization to achieve maximum sensitivity for a target application.

Modern FPGAs have become competitive platforms for System-on-Chip (SoC) designs resulting in the emergence of Network-on-Chip (NoC) paradigm as a promising solution for FPGAs interconnects problems. This paper proposes a high throughput FPGA-oriented router architecture denoted by Dual Split-Merge (DSM). The proposed architecture divides the router into two independent internal routers handling each network dimension. The division allows an incoming packet to face only half the complex logic and half the arbitration, increasing both the network throughput and the maximum operating frequency. Each internal router utilizes split and merge primitives that obviate the need for a switch crossbar and a switch allocater, decreasing the router area. The implementation results show the significant improvements in performance of the proposed router over the existing ones. The proposed router has a higher throughput than all other routers and a small network latency. A 4 × 4 network of DSM routers achieves a maximum throughput of 4.6 Gflits/s on Virtex-6 FPGA.

FPGA has become a favorable platform for Systems-on-Chip (SoC). As SoC gets larger, a Network-on-Chip (NoC) emerges as a promising solution for communication problems among SoC's modules. Consequently, the importance of NoC on FPGAs has increased, not only to solve SoC's communication problems but also as a solution to FPGA's slow interconnects and to simplify Partial Dynamic Reconfiguration (PDR). Hard NoCs have better performance and consume less area and power than Soft NoCs. However, they are not configurable and they lead to a wasted area when the network is not in use. This makes the design of hard NoCs more critical to get an optimum performance while minimizing the wasted area as much as possible. In this paper, various NoC design parameters are evaluated to find the best-fit parameters that can be used in the non-configurable hard NoC design. In addition, different router architectures are investigated to select the optimum one for hard NoCs. Moreover, an efficient novel method for embedding the hard NoC inside the FPGA is proposed. The proposed NoC reduces the wasted area by using minimum and shareable resources. The NoC provides the FPGA with a high-performance communications infrastructure at a negligible cost. A total throughput of 0.33/1.3 Tbps (at a 32/128-bit flit width) is achieved on 65 nm technology at an added cost equivalent to the area of only 16/32 logic clusters.

The general structure of a multilevel multistate dc–dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub- ${\mu }\text{s}$ range with output voltage ripples below 50 mV.

Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different error recovery techniques are used to tolerate the process, voltage, and temperature variations. These techniques reduce the throughput by scaling down the frequency or flushing and restarting the errant pipeline. A resilient microarchitecture is introduced in this paper to tolerate the induced delays generated by the voltage scaling and the process, voltage, and temperature variations. This resilient microarchitecture detects and recovers the induced errors without flushing the pipeline and without scaling down the operating frequency. A resilient 16 b $\times16$ b MAC unit was fabricated using Global Foundry 65-nm technology with 18.26% area overhead and upto $1.65\times $ speedup. At the typical conditions, the maximum frequency of the conventional MAC unit is about 375 MHz while the resilient MAC unit operates correctly at a frequency upto 620 MHz. In case of variations, the resilient MAC unit tolerates induced delays up to 50% of the clock period while keeping its throughput equal to the conventional MAC unit’s maximum throughput. At 375 MHz, the resilient MAC unit is able to scale down the supply voltage from 1.2 to 1 V saving about 29% of the power consumed by the conventional MAC unit.

The design and photonic generation of power-efficient impulse radio ultra-wideband (IR-UWB) waveforms is a challenging step in the design and development of IR-UWB over fiber (IR-UWBoF) systems with combined optical and wireless transmission. In this paper, the definition of the spectral power efficiency (SPE) and its associated optimization problem are reformulated. Based on this reformulation, a theoretical upper bound for the SPE is derived and applied to two of the most common types of photonically generated IR-UWB waveforms. Accurate closed-form analytical expressions for the SPE upper bounds of these two waveform types are obtained and optimized. The analytical framework presented in this paper can be extended and applied to other waveform types. Simulation results show excellent agreement with the analytically obtained expressions. Accordingly, these analytical expressions can be used as reliable guidelines for precise and efficient design of practical IR-UWBoF systems that guarantee optimal design, generation, and distribution of IR-UWB waveforms.

This brief presents a new low-power miniature instrumentation amplifier based on the operational floating current conveyor (OFCC). The OFCC is a general-purpose current mode device capable of realizing all functions as an operational amplifier. The proposed OFCC is designed and implemented in both TSMC low-power 90-nm and UMC high-speed 130-nm CMOS technology for use in low-voltage applications. A single supply of 0.4 V is used to reduce the power consumption. The design utilizes the energy-efficient subthreshold region. A self-cascode technique is used to enhance the tracking capability of the OFCC. Post-layout simulation and Monte Carlo analysis show promising results. The current mode instrumentation amplifier in 90 nm occupies 0.023 mm2 while consuming $11~ {\mu }\text{W}$ with 14 kHz gain-independent bandwidth and common mode rejection ratio (CMRR) of 76 dB. The 130-nm design exhibits input referred noise of $1.1~ {\mu }\text{V}_{\text{RMS}}$ for a bandwidth of 0.07–150 Hz while consuming $14~ {\mu }\text{W}$ and CMRR of 65 dB with 100-kHz bandwidth with chip area 0.021 mm $^{{2}}$ .

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4 V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90 nm and UMC 130 nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.

Efficient utilization of the extremely limited available power of impulse radio ultrawideband (IR-UWB) waveforms can significantly extend their wireless reach in the wireless transmission chain of IR-UWB over fiber (IR-UWBoF) systems. In this letter, the two most common types of photonically generated IR-UWB waveforms are considered and accurate closed-form analytical expressions for the bit rate—distance relationship in the wireless transmission chain of IR-UWBoF systems are developed. These analytical expressions are verified by simulations and optimized such that the wireless transmission distance of IR-UWB waveforms is maximized under the Federal Communications Commission spectral constraints.

Careful design and photonic generation of power efficient impulse radio ultra wideband (IR-UWB) waveforms by shaping their spectra is one of the most important challenges in the analysis and design of IR-UWBoF systems. Throughout this letter, theoretical expressions for the signal to noise ratio of IR-UWB waveforms in terms of their spectra are developed and optimized. Two common types of IR-UWB waveforms are considered. Numerical simulations results show excellent agreement with the obtained theoretical expressions.

The fact that security is not the main functionality of an IoT device means that even lesser portion of its computing power is available for security. Security measures implemented in traditional computers such as cryptography, present a challenge from this context when applied in IoT devices. Different algorithms have been presented in the literature that meet IoT requirements and yet maintain the needed security level. Most of the studies have focused on popular algorithms, especially AES finalists. However, more IoT oriented algorithms have been presented to provide better performance in terms of power and capacity, those are known as lightweight cryptographic algorithms. PRESENT as one of the lightweight cryptographic algorithms is the main focus of this study. The algorithm has been implemented using MATLAB, ASIC and FPGA flows. Lowest achievable power consumption is 120.9 µW at throughput of 20.64 Mbps for the ASIC. For the FPGA, best achievable results was for 16 s-box design utilizing a power of 225.95 mW and 352 LUTs.

This work aims to investigate the difference in the electrical parameters e.g. Impedance, capacitance and permittivity. Those parameters were investigated for different cells such as the dead and viable Normal Human Bone Osteosarcoma Epithelial (U2OS) Cells at different frequencies using micro-electrical impedance spectroscopy $(\mu \mathrm{EIS}). >\mu \mathrm{EIS}$ defines the electrical parameters of normal U2OS cells inserted between sensing microelectrodes. The frequencies of the spectrum used to define the electrical parameters ranges from 1kHz to 3MHz.

In this work, silicon-based plasmonic nanoantennas was realized. Using silicon instead of metals as the material of choice in building such nanoantennas is advantageous as it enables the integration of nanoantennas-based structures into integrated-optoelectronics circuits built using the standard fabrication techniques in the electronic industry. It also allows for low cost mass production of the proposed devices. Upon light incidence on an array of nanoantennas, Localized Surface Plasmon Resonance (LSPR) is generated which causes an enhancement in the localized field inside the structure and in the near field zone. The enhanced localized field is manifested as an enhancement in the absorbed as well as the scattered field. Varying the surrounding material causes variations in the wavelength of the enhancement peak as well as the enhancement level itself. Hence, sensors can be built to facilitate sensing molecules with its characteristic vibrational transitions. In this paper, dipole and bowtie silicon nanoantennas are investigated. It is found that when using silicon with high excess carrier concentrations as the material of choice, the enhancement occur in the mid-IR spectral range which is red shifted compared to the enhancement produced when using metal such as gold or silver. Working in mid-IR is advantageous for sensing applications as the characteristic vibrational transitions of the majority of bio-chemical molecules happens in the mid-IR.

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (Vd). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.

The reliability of the synchronous circuits is a critical issue due to the continuous scaling of the fabrication technology. Process, voltage, and temperature (PVT) variations increase the probability of violating the timing constraints. Different techniques are used to tolerate the variability and relax the timing of the circuits. Error recovery system using taps (ERSUT) is introduced in this brief to tolerate the PVT-variation-induced delay by detecting and tolerating the error without flushing the pipeline. The faulty critical stages, due to PVT variations, are healed by borrowing slack from the next stages. As a test case, ERSUT is applied to 16 $\times$ 16-b MAC unit (currently in fabrication using Taiwan Semiconductor Manufacturing Company (TSMC) 90-nm technology). Without flushing the pipeline, the MAC unit tolerates 20% of its clock period as an additional induced delay. The proposed approach has about 20.93% overhead of area and 25.7% overhead of power.

In this paper we report on the design of a frequency compensation system for AlN-on-Si MEMS reference oscillator to replace temperature compensated crystal oscillators (TCXOs) in cellular handsets. A 76.8MHz, 105ppm Temperature Stable, AlN-on-Si MEMS Oscillator is designed to demonstrate the frequency compensation scheme. Double layers of SiO 2 are used for passive temperature compensation. The oscillator consumes 850µA, with phase noise of -127dBc/Hz at 1kHz frequency offset. Temperature drift errors and initial frequency offset of ź 8000ppm are combined and further tackled electronically. A simple digital compensation circuitry generates a compensation word to a 21-bit MASH 1-1-1 ΔΣ modulator included in LTE fractional N-PLL for frequency compensation. Temperature is sensed using 4.6µA, 11.5 bit temperature to digital converter TDC with resolution of 0.1°C in 100ms conversion time. The paper presents the first AlN-on-Si oscillator platform with ź 0.5ppm frequency stability over temperature ranges from -40°C to 85°C. The system runs on 1.8V supply in 32nm CMOS.

Memristor, the missing fourth element predicted by L. Chua, has recently been in the research focus since HP Lab reported the first TiO 2 thin film memristor realization. The nano-scale geometry size of the memristor makes it difficult to control its dimensions due to the process variation incurred in the fabrication process. This process variation results in yield degradation in the memristor-based memories. This yield degradation is more severe when the memristor device is used as a multi-valued memory element. In this paper, the impact of the process variation on the memristor-based memory yield is investigated for the 1-bit, 2-bit, and n-bit memristor memory element. In addition, two approaches are proposed to improve the memory yield. Therefore, the main objective of this work is to introduce a statistical yield simulation flow to calculate the memory statistical yield under process variations and investigate the effect of different design knobs on this statistical yield regardless of the memristor models and the process variation models used. Simulation results reveal that for 1-bit memristor-based memories, the nominal write voltage should be increased by 30% and the nominal threshold value (i.e., the midway memristance value between the memristor ON resistance and the memristor OFF resistance) should be increased by 65% to achieve the maximum yield. Finally, the paper lists the minimum memristor size that should be used to achieve a 99.9% memory yield for n-bit memories. These results show how the process variation imposes limitations on the minimum memristor device size when multi-valued memories are to be designed.

Modern wireless devices require a compact wireless receiver that can access all the available services with fewer bulky off-chip passive components. This advocates the need for multi-band multi-standard receivers. This paper proposes a reconfigurable such receiver front-end controlled by its driving clocks. The receiver adopts charge sampling and impedance translation techniques. Its driving clocks are adjusted based on the targeted frequency. The receiver is tested over the existing standards specifications: GSM 2G (850MHz, 900MHz, 1.8GHz and 1.9GHz), UMTS 3G (850MHz, 1.8GHz, 1.9GHz and 2.1GHz), Bluetooth (2.4GHz) and LTE (700MHz?5GHz) and Wi-Fi (2.4GHz and 5GHz). The proposed front-end architecture achieves NF of 8dB, out-of-band IIP3 of 0dBm and in-band IIP3 of -5dBm across the tested frequencies in 65nm CMOS technology. The design occupies 0.45mm2.

In this paper, we demonstrate the use of triboelectric nanogenerator (TENG) as a mean of mechanical light triggering to control InGaN-based light-emitting diodes (LEDs). Light extraction from the LED is two successive steps process. First, the voltage produced by the TENG is used to control the gate-to-source current of a MOSFET transistor through adjusting the transistor channel width and length. The second step is forwarding the drain-source current resulting from MOSFET transistor to the LED as its injection current to induce spontaneous emission from the LED surface to the air. Three LED colors are considered: red, green and blue. Significant emitted power from these InGaN-based LEDs in the RGB wavelength band is observed for both P-MOSFET and N-MOSFET transistor configurations. The emitted optical spectrum is controlled by optimizing the combined TENG-MOSFET-RGB LED geometry; dimensions and the bias voltage between the drain and source terminals of the MOSFET transistor. With recent advances in TENGs as an energy harvesting technology, it is expected that this study offers an approach to enhance the light extraction of various LED devices. With the enhancements in the performance of optoelectronic devices, the field of tribo-phototronics has attracted more attention, and in this work, we introduce the first theoretical framework, to the best of our knowledge, based on finite element modeling. This study provides significant insights into the working principles of tribo-Phototronic devices as well as guidelines for future device design.

Effective compression guarantees that IoT will continue spreading to cover various devices. High Efficiency Video Coding (HEVC), also known as H.265, is the most recent video coding standard; it introduces new coding methods compared to older popular standards. Such a change has a great impact on both encoder complexity and speed as it provides bitrate reduction up to 50% compared to H.264/AVC while keeping the same video quality. Unfortunately, HEVC is computationally intensive, relatively slow and power consuming. Therefore, hardware implementation is desirable to get over these drawbacks. This work introduces an efficient implementation of HEVC encoder/decoder Algorithm targeting low power solutions in order to be compatible with the IoT devices. Verflog language was chosen as an HDL to carry over the implemented design to hardware. In addition, an analytical comparison of the implemented hardware and the related work is presented. The comparison is based on encoding performance such as power consumption and compression speed.

In this paper, a low-energy rate 1/2 successive cancellation (SC) decoder hardware architecture is proposed for Internet of Things (IoT) applications. Arikan’s SC decoder and different optimized versions of it are implemented in ASIC flow. Hardware optimizations are applied to the conventional SC architecture, including the removal of frozen bits driving blocks, resource sharing between f and g blocks and the removal of log-likelihood magnitude computation in the last stage. Synthesis results show that these optimizations provide 38.7% saving in energy/bit consumption, 83% saving in area and 68.0% increase in throughput for 64-bit conventional SC decoder and up to 79.5% in 1024-bit implementation. The synthesis results are compared with the literature, and the results show that the proposed 64-bit SC architecture gives less energy/bit consumption and area. Moreover, linearly scaled 1024-bit synthesis results predict a middle-ground performance of the proposed architecture compared to the literature, hence suggesting the proposed structure to IoT applications, especially small packet size applications.

This paper presents a detailed analysis of the security characteristics of chaotic Baker Maps and presents suggestions to improve its security characteristics. The number of possible keys for a baker map is derived using closed form solutions. It is shown that for a reasonable size baker map a large number of possible keys exists, making a brute force attack infeasible. However, it is shown that baker maps have very poor security characteristics under known attacks. Specifically, a baker map of size $N$ can be broken in $N$ iterations or less. This weakness can limit the usefulness of using baker maps as is in encryption. Modified techniques are needed to improve the security of baker maps, some of which are suggested in this paper.

Lab on a Chip (LOC) applications are taking the world by storm. This paper proposes a mixed mode interface circuit for LOC applications for Bioimpedance measurement. The interface circuit consists of a low noise instrumentation amplifier and an analog to digital converter. The proposed interface circuit utilizes the benefits of both current mode and voltage mode circuits. The design of the instrumentation amplifier uses a second-generation current conveyor to provide the low noise and high gain required to acquire the weak signal from the electrodes. The IA provides a maximum gain of 55.6 dB with 2 MHz bandwidth. A second order Sigma Delta Modulator with a maximum sampling rate of 128 MS/s provides the output digital bit stream capable of reaching a resolution of 11 bits for an input sinusoidal with 50 kHz frequency. The use of a buffered comparator allows the relaxation on the slew rate requirement while maintaining a high sampling rate. The full system power consumption is 5.5 mW with a chip area of only 0.0153 mm2.

In this chapter, we try to highlight the importance of hardware security in modern systems. Increasingly we are connected to loosely controlled networking infrastructures such as IoT and intelligent transportation networks. In such networks, users are connected in an ad hoc style, which makes users'authentication and identity management a very complex problem. Modern security frameworks, especially in battery-based devices, rely on hardware security to protect confidential information and secret data. The ICs used in such systems must be protected against different hardware attacks, such as side-channel attacks and HT insertion.

In this paper, we demonstrate a plasmonic planar lens structure that can achieve subwavelength focusing of the infrared electromagnetic radiation. The lens is composed of metallic binary slits with different dielectric fillings. The index modulation approach of the filling materials is used to achieve phase modulation of the wavefront of the incident wave. Using this approach, we could achieve a phase range of 0.43π. The structure can focus the incident infrared wave in the subwavelength scale. The focal length attained is 44.69 μm and the achieved Full width at half maximum (FWHM) is 4.28 um for an incident infrared wave of wavelength 8 um. The transmission through the structure is 25.64 % at the design wavelength. The used metal is copper and the dielectric filling materials are silicon and air. Copper has lower losses in the infrared range than the traditional metals used in visible Plasmonics. Silicon has a higher melting point than the common dielectric materials used in refractive index modulation of the visible Plasmonic lenses. This temperature stability is a very important feature when working in the infrared domain. Besides being specifically suitable for the infrared range, copper and silicon are also CMOS compatible. Therefore, the proposed structure is suitable for integration in many potential infrared applications such as thermal imaging, medical diagnosis, thermal photovoltaic cells and heat harvesting. In addition, the fact that many molecules have unique absorption spectra or signature in the infrared range would facilitate the analysis and study of many materials and biological molecules using infrared miniaturized spectrometers.

Optical interconnects have been proposed to be the next generation interconnect solution to overcome the impending interconnect bottleneck. Large optical devices have hindered integration of electrical and optical components. Plasmonics have enabled nanophotonic components with sub-micron scale optical devices with similar size range as electronics and they promise to bridge the size gap between optical and electrical components. Surmounting research is suggesting that the electronics industry is starting to accept more variety materials in the fabrication process, the most important of which is graphene. The modulator is composed of a thin layer of silicon nitride – a few nm thick – sandwiched between two graphene sheets that are both electrically connected to the signal. Thin Al2O3 layers separate the graphene sheets from the ground electrodes on top and bottom. The electric field generated by applying a maximum of 5V on the graphene sheets changes the fermi level of graphene to switch between a highly lossy metal-like material and a dielectric material. Operating in the mid infrared regime, around 5 μm wavelength, when the Fermi level is located in the band gap, optical absorption is high. When the Fermi level is located away from the bandgap, absorption is minimized. Simulations show that the modulator exhibits over 7 dB / μm extinction ratio and less than 0.1 dB / μm propagation loss. By designing for 3 dB extinction ratio and less than 0.1 dB propagation loss, the footprint of the modulator is only 80 nm x 400 nm for feasible integration in future electronic chips without competing for space.

This paper proposes an automated control system which is necessary for Lab-on-chip (LOC) applications. The control system consists of two subsystems. The first subsystem is the signal generator which is required to generate four out-of-phase signals with phases 0°, 90°, 180° and 270°. The signal generator is based on two Analog Devices AD9851 Direct Digital Synthesizers (DDS). The second subsystem of the system is the data acquisition system which is needed to acquire the output signals from the LOC. The data acquisition subsystem is implemented using Saleae Logic Pro 8. The signal generator provides a bandwidth of 5 MHz with four perfectly synced sinusoidal signals. The data acquisition also provides the same bandwidth with sampling rate of 50 MS/s. The control interface for the complete signal is implemented using National Instruments LabVIEW software which automates the whole system and facilitate further processing on the output signals.

This paper presents a low power instrumentation amplifier (IA) for the use in Internet of Things (IoT). A modified topology based on the INA321 by Texas Instruments of the two-opamp IA is used for its higher CMRR. The main design constraints are low power consumption and low noise. Two stage topology opamp is used for its capability of operating from a low supply voltage. Self-cascode technique enhances the open loop gain and allows the use of indirect compensation reducing the capacitor size. The drawback is reduced bandwidth however not a concern as many IoT applications exhibit narrow bandwidth. Post layout simulation is performed using Cadence Virtuoso 6.1.5 and TSMC 65 nm node. The designed opamp consumes 28.8 nW from a 0.4 V supply. Exhibits an open loop gain of 52 dB with phase margin 90 degrees. The IA has a fixed gain of 24 dB and bandwidth of 11 kHz. Common mode rejection of 83 dB is achieved. Total power dissipation is 89 nW.

This work studies the fundamental mode and dispersion relation of a slot waveguide made of intrinsic silicon as the high index region and Air as the low index region by solving the full vectorial wave equation using vectorial finite element method. The objective is to identify the effect of dynamically inducing high excess carrier concentrations in silicon on the slot mode and it dispersion. Tracking the slot mode over a range of wavelengths reveals a reduction in the slot mode effective index upon introducing high concentration of excess carriers. This can be exploited in the dynamic tuning of a silicon slot waveguide dispersion and hence the operation of any sensor based on such waveguide by dynamically generate excess carrier at runtime.

High reflection losses combined with low absorption capabilities and high velocity surface recombination are the main problems that deteriorate the efficiency of thin silicon solar cells. Therefore, Low cost and easy scalable fabrication of wide band, angle and self-cleaning antireflection coatings are of great importance for different optical applications especially solar cells. Random textured silicon nanocones are fabricated through electroless metal assisted chemical etching (EMACE) combined with ambient oxidation. Theoretical studies using Finite difference Time Domain (FDTD) simulation guided the experimental procedures in terms of dimensions and tolerance to reach the optimum dimensions and superior optical properties. The Optical numerical and experimental studies are revealed wide antireflection properties and strong trapping effects up to 60° through the entire visible wavelength. The textured structure modified the hydrophobicity of the solar cell into hydrophobic surface with self-cleaning properties.

This article is a survey of the most common lab-on-a-chip techniques based on CMOS technology. It also presents different microfluidic packaging techniques that are used in the currently used lab on a chip based on CMOS technology.

In this paper, a novel library-based macro-modeling technique is developed to extract equivalent RLGC model which is spice compatible for TSV arrays of any size N×M. The built model accounts for Through Silicon Via (TSV) parasitic dependence on the array structural parameters and the frequency dependent properties of the silicon substrate. The developed macro-model constructs an equivalent parasitic matrix that could be used by circuit simulators to estimate the maximum signal frequency as well as noise in the TSV array. The key idea of the macro-model is to partition any given TSV arrays into smaller and fixed-size arrays. Smaller arrays are characterized and their parasitic are stored in the library. Using a divide and conquer technique, the final solution of the TSV array is produced. A detailed comparison of the proposed macro-modeling technique against the parasitic extracted by microwave simulation, for different structures with different sizes, shows a maximum error of 10% and an average error of 5%. Furthermore, the performance of library based macro-modeling is order of magnitude faster than the microwave simulation.

In this paper, we propose a detailed study of various novel waveguides made using doped silicon at the mid-infrared (MIR) range. These waveguides support a plasmonic-like mode with nanoscale confinement in the MIR. We also demonstrate a simple mechanism for tuning the plasma resonance through controlling the doping level of silicon. Moreover, the dispersion characteristics of the doped silicon devices are analyzed for different applications at the MIR region. We also investigated various phenomenon such as negative dispersion, which can be utilized for slow light and metamaterial applications, and epsilon-near-zero characteristics that can be used for extraordinary transmission. The MIR dispersion is studied thoroughly for the slot structure and the rectangular shell structure. The potential for biological and environmental sensing for the aforementioned structures is investigated as well. In addition, we demonstrated the use of the waveguide as a slow light medium; this was facilitated as the dispersion relations reached giant values in the order of $10^{5}$ at the resonance.

Nanoscale trigate FinFET with channel lengths down to 9.7 nm as projected by the 2013 International Technology Roadmap of Semiconductors (ITRS-2013) are simulated by means of quantum corrected 3-D Monte Carlo technique in the ballistic and quasi-ballistic regimes. Ballisticity ratio (BR) is extracted and found to reach values as high as 90% at $L_{G}=9.7$ nm. The impact of the ITRS-2013 scaling strategy on the BR, and ON-/OFF-states is discussed. Forward and backward electron velocity components are extracted along the channel to analyze the electron transport in detail. Velocity profile is found to be characterized by two critical points along the channel, each is associated with a change in the electron acceleration showing the physical significance of the off-equilibrium transport with scaling the channel length.

This paper reports on the design of a low phase noise 76.8MHz AlN-on-silicon reference oscillator using SiO 2 as temperature compensation material. The paper presents profound theoretical optimization of all the important parameters for AlN-on-silicon width extensional mode resonators, filling into the knowledge gap targeting the tens of megahertz frequency range for this type of resonators. Low loading CMOS cross coupled series resonance oscillator is used to reach the-state-of-the-art LTE phase noise specifications. Phase noise of -123dBc/Hz at 1kHz, and -162dBc/Hz at 1MHz offset is achieved. The oscillator?s integrated root mean square RMS jitter is 106fs (10kHz to 20MHz), consuming 850µA, with startup time of 250µs, and a figure-of-merit FOM of 216dB. This work offers a platform for high performance MEMS reference oscillators; where, it shows the applicability of replacing bulky quartz with MEMS resonators in cellular platforms.

In this paper, a fitting model to the propagation constant and the losses of Metal–Insulator–Metal (MIM) plasmonic waveguide is proposed. Using this model, the modal characteristics of MIM plasmonic waveguide can be solved directly without solving Maxwell's equations from scratch. As a consequence, the simulation time and the computational cost that are needed to predict the response of different plasmonic structures can be reduced significantly. This fitting model is used to develop a closed form model that describes the behavior of a plasmonic nano-filter. Easy and accurate mechanisms to tune the filter are investigated and analyzed. The filter tunability is based on using a nonlinear dielectric material with Pockels or Kerr effect. The tunability is achieved by applying an external voltage or through controlling the input light intensity. The proposed nano-filter supports both red and blue shift in the resonance response depending on the type of the used non-linear material. A new approach to control the input light intensity by applying an external voltage to a previous stage is investigated. Therefore, the filter tunability to a stage that has Kerr material can be achieved by applying voltage to a previous stage that has Pockels material. Using this method, the Kerr effect can be achieved electrically instead of varying the intensity of the input source. This technique enhances the ability of the device integration for on-chip applications. Tuning the resonance wavelength with high accuracy, minimum insertion loss and high quality factor is obtained using these approaches.

Internet of Things (IoT) is the field that connects things together and to the Internet, letting them exchange data, communicate with each other and interact with the human. Recently, it has been widely used to go beyond the machine to machine (M2M) communication and covers variety of protocols and applications that facilitates people's way of living. However, many challenges still hinder its advances, especially security and power issues. In this paper, a comparative study for IoT architectures, platforms and applications is presented with a case study to illustrate the main IoT concepts and levels of abstraction. Then, a Strengths – Weaknesses – Opportunities – Threats (SWOT) analysis is presented to assess the present and the future of IoT.

Neural interfaces are systems operating at the intersection of the nervous system and an internal or external device. Neuro-stimulator is one of the most important neural interfaces used to help those who experience epileptic seizures. To use this stimulator efficiently, seizure should be detected at the right time. Seizure detection is basically founded on digital signal processing by monitoring certain features of the intracranial electroencephalogram. Many of the previous researches are directed to study the detection efficacies using different systems, however, a few of them study the feasibility of implementing these systems over a computationally limited power implantable platforms. In this paper, five time-domain features and three wavelet-domain features are investigated. Following that, a high accuracy seizure detection algorithm is presented with efficient power consumption which makes it suitable for implantable neural systems. The experiment results show that the presented method achieves a sensitivity, specificity, and accuracy of 92.64%, 99.29%, and 99.16% respectively for long-term iEEG seizure detection. The area and power results are obtained from implementing the algorithms on Xilinx Spartan-6 XC6SLX45T FPGA.

This paper presents a new design methodology of time-based capacitance-to-digital converters (T-CDCs). The sensor capacitance is the load capacitance of a voltage-to-time converter (VTC) circuit based on current starved inverters. The VTC circuit used has improved sensitivity, linearity and dynamic range. The time delay provided by the VTC circuit is buffered providing a time pulse proportional to the sensor capacitance (Cs). Thus, the VTC circuit becomes a capacitance-to-time converter (CTC) circuit. The time pulse is then digitized using a time-to-digital converter (TDC) circuit providing an output digital code proportional to the sensor capacitance. The output digital code is PVT calibrated using a reference capacitor (C ref ). The proposed T-CDC system is a time-based ADC, but with the sensor capacitance as the load capacitance of the used VTC circuit and the input voltages of the current starved inverters in the VTC circuit are fixed and used for biasing. The prototype of the proposed T-CDC is implemented in UMC 130 nm CMOS technology. The T-CDC system is clocked with a 1-MHz clock signal to the VTC circuit. Experimental results show that for a 1 ns counting cycle of the TDC circuit, the system achieves a 8.5-bit resolution and consumes 20 μW with an energy efficiency figure-of-merit (FoM) of 55 fJ/step and a conversion time of 1 μs.

Reconfigurability of Field Programmable Gate Array (FPGA) makes it one of the most promising approaches in the implementation of reconfigurable systems. Partitioning the reconfigurable system to many Reconfigurable Modules (RMs) and allocating them into Reconfigurable Regions (RRs) on the FPGA is a challenging task for the system designer. Partitioning choices impact the area efficiency and the time of reconfiguration of the reconfigurable systems. In this paper, different partitioning techniques are studied and evaluated according to their impact on reconfiguration time and the area utilization. Also, a new proposed Dynamic Partial Reconfiguration (DPR) tool flow is presented that automates and optimizes the partitioning procedure based on a graph clustering algorithm, modifies the design's HDL files as per the partitioning results, and implements a routing switch to dynamically change routing between Reconfigurable Regions (RRs) during reconfiguration.

Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) becomes a demanding feature by many applications for its ability to add more flexibility over runtime phase. Recently, implementation designs which utilize DPR are easier than before. However, techniques that FPGAs use to perform DPR (like ICAP and JTAG) encounter a performance bottleneck; only one DPR is allowed at a time. In this paper, we present a state-of-art NoC-based FPGA simulator, which supports partial dynamic reconfiguration simulation. Design limitations and performance degradations of using DPR on NoC-based FPGA are estimated using NoC-DPR simulator. Experiments are carried out using NoC-DPR simulator to measure the reconfiguration time overhead by increasing number of simultaneous DPRs on FPGA fabric. It is shown that the overhead of reconfiguration time is increased exponentially with increasing the number of carried out simultaneous DPRs. However, DPR of NoC-based FPGA can enhance performance compared to DPR of normal FPGAs with some trade-offs.

Recently, most of researchers focus on low-power design for monitoring, and controlling different smart platforms. Generating reference voltages for power conditioning of these systems is one of the main design challenges of these systems. Therefore, bandgap reference (BGR) is required for providing a temperature, and supply independent reference voltage. This paper presents a CMOS lowvoltageself-startup BGR circuit with improved power supply rejection ratio (PSRR). The proposed self-startup BGR circuit is based on the relation of a proportional to absolute temperature (PTAT), and complementary to absolute temperature (CTAT) references. A low-power BGR is implemented in 0.13 µm CMOS technology. The implemented BGR generates a reference voltage of 0.8 V, and consumes 9.5 µA form 3.3 V battery. Moreover, it achieves a high PSRR of 76 dB at 1KHz, while the temperature coefficient is 20 ppm/℃.

Memristors are novel devices that are used to replace SRAMs as memory arrays in the near future. Therefore, this work investigates the impact of radiation on memristorbased memory. Moreover, this work aims at calculating the critical charge that causes soft errors due to an alpha particle or a neutron strike in HP memristor using analytical models. These models are verified by using Cadence Spectre simulations. The TEAM model is utilized in the model derivation and the verification. Studying the impact of radiation on memristors is very essential in the migration step from SRAM memories to memristor-based memories. This work will help memristorbased memory arrays designers predict the impact of soft errors on their memory design and find methods to mitigate these soft errors.