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A 0.8-V Bluetooth 5 (BT5) digitally intensive transceiver with a phase-tracking RX and a digital TX in 40-nm CMOS is presented. For the phase-tracking RX, a hybrid loop filter with a loop-delay compensation is proposed to suppress digitally controlled oscillator (DCO) sidelobe energy, enhancing interference resilience. To facilitate the DCO-based phase-tracking RX for the reception of BT5 signals, a corresponding digital baseband is implemented with a carrier frequency offset (CFO) calibration to remove the initial static CFO error during the preamble, while an automatic frequency calibration tackles the frequency drift during the payload. An all-digital phase-locked loop (ADPLL)-based digital frequency-modulation (FM) interface shared between TX and RX provides a precise deviation frequency control, ensuring the quality of signal transmission and reception. In the RX mode, the chip consumes 2.3 mW from a 0.8-V supply, achieving a figure of merit (FoM) of 180 dB with −91-/−94-dBm sensitivity at 2/1 Mb/s. In the TX mode, it consumes 6.1 mW when delivering a maximum 1.8-dBm output power, resulting in 25% TX system efficiency.

In this paper, we propose a new scheme to directly power a 4.9-5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/Hz which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a $10\times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $\Sigma \Delta $ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply).

This letter presents an ultrawideband (UWB) radar for occupancy and vital signs detection. The proposed burst-chirp operation achieves $> 30\times $ power reduction and abundant margin for the UWB spectrum regulations. With the proposed Domino chirp generation and time-domain predistortion, the radar has a fast chirp slope of 0.7 GHz/40 $\mu \text{s}$ and a low RMS error of 0.5 MHz. Fabricated in a 40-nm CMOS process, the presented radar consumes a record-low power of 680 $\mu \text{W}$ and can detect human respiration and heartbeat up to 15 and 5 m, respectively.

Class-G efficiency enhancement of switched-capacitor (SC) power amplifiers (PAs) requires the power management unit (PMU) to have two high-current power supplies. This paper presents a Class-G efficiency enhancement that only requires one single high-current power supply with a lower bandwidth requirement, significantly simplifying the PMU. The system analysis shows that a transmitter with a resolution of 13 bits and a sample rate of $F_{RF}/2$ meets the requirements of the Cat-M1 and Cat-NB1 standard. The presented PA consists of a number of parallel SC cells. Each cell can be configured in two output-power modes, using only a single supply. At 807 MHz, the peak output power is 27.1 dBm, with an efficiency (PAE) of 33.3%. The efficiency at −6 and −12 dBFS is 22.5% and 14.4%, respectively, which is an improvement of $1.3\times $ and $1.7\times $ compared to Class-B. The 13-bit resolution enables a power-control range for Cat-M1 and Cat-NB1 signals of >63 dB. In that range, the error vector magnitude (EVM) is

An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed start-up technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a $13\times $ start-up time reduction and an overall power of $95\mu \text{W}$ for a 24-MHz crystal oscillator at 1 V. A fully autonomous feedback loop detects the oscillators envelop and adjusts the load capacitance at start-up. Thanks to the low-power start-up circuits, both the start-up time and the start-up energy are reduced. In addition, the robustness and versatility of the proposed method is verified by measuring quartz crystals with different frequencies and quality factors, as well as measuring against temperature, supply voltage, and load capacitance variations.

This session presents two different approaches to highly efficient wireless communication. The first two papers focus on impulse-radio ultrawideband communication, whereas the following three papers present different implementations of wake-up receivers with low power consumption, high-sensitivity and improved interference rejection.

We have seen an emergence of quantum-computing activity in recent years from an uptick of startups to investments at established companies. Yet, there is more to quantum systems than simply computing. In fact, quantum systems by themselves do not work, and classical electronics are needed to interface with quantum devices. In this forum, we look at electronics, in particular CMOS electronics, for use in combination with quantum devices from the designer’s perspective. We explore these systems from specifications to testing, often at cryogenic temperatures, and discuss recent successes and future trends.

The recent popularity of indoor-localization applications such as secure access and asset tracking has led to growing interest in accurate RF-based ranging solutions. Impulse-radio ultra-wideband (IR-UWB) is a promising solution for accurate ranging due to its wideband 0peration. The recently released IEEE 802. 15.4z standard [1] improves upon the security of ranging and mandates a coherent operation with higher mean pulse-repetition frequencies (mPRF), in comparison to the legacy standard IEEE 802. 15.4a. The next generation IR-UWB devices demand ultra-low-power operation while meeting the strict spectrum regulations to operate worldwide in C and X bands (4 to 10GHz). The prior-art coherent IR-UWB transmitters either consume very high power [2] or result in high spurious emissions in adjacent channels due to poor sidelobe suppression [3 –6]. In this work, an asynchronous polar transmitter is proposed that consumes 4.9mW active power with an output power spectral density (PSD) of -41.3dBm/MHz and a sidelobe suppression of over 28dBrin IEEE 802. 15.4zl24.8MHzmPRF mode, channel 9 (7987.2MHz). Further, we demonstrate the use of an injection-locked ring oscillator (IL-R0) with fine-grained duty-cycling of the TX chain to achieve state-of-the-art power consumption for mPRFs from 3.9MHz to 124. 8MHz while maintaining coherent operation over the packet.

A low-power IEEE 802.15.4z high-rate PHY (HRP) compatible coherent transmitter is described. The proposed transmitter uses a digital polar architecture with fixed amplitude steps in the power amplifier and asynchronous time-discrete pulse shaping. The pulse-shaping unit consists of a finite-impulse response (FIR) filter using current-starved inverter-based delay taps that can be calibrated on-chip. An injection-locked ring oscillator (ILRO)-based frequency synthesis enables wideband operation from 3- to 10-GHz frequency bands. The ILRO also allows for duty-cycled coherent mode operation with 2–4-ns phase locking time and binary phase modulation is applied directly on the oscillator. The on-chip digital front end enables duty cycling (DC) of analog front-end modules with a granularity of 2 ns. Implemented in 28-nm CMOS process, this chip is measured to consume 4.9-mW power in nominal mode with IEEE 802.15.4z high pulse repetition frequency (HPRF) compatible data rate of 6.81 Mb/s compliant with major spectrum mask regulations for channels 5 and 9. With DC of the oscillator enabled in the energy-efficient mode, a power consumption of $430~\mu \text{W}$ is achieved for packets compatible with legacy pulse-position-modulated IEEE 802.15.4a standard with a data rate of 27.2 Mb/s.

This paper presents a millimeter-scale crystal-less wireless transceiver for volume-constrained insertable pills. Operating in the 402-405 MHz medical implant communication service (MICS) band, the phase-tracking receiver-based over-the-air carrier recovery has a ±160 ppm coverage. A fully integrated adaptive antenna impedance matching solution is proposed to calibrate the antenna impedance variation inside the body. A tunable matching network (TMN) with single inductor performs impedance matching for both transmitter (TX) and receiver (RX) and TX/RX mode switching. To dynamically calibrate the antenna impedance variation over different locations and diet conditions, a loop-back power detector using self-mixing is adopted, which expands the power contour up to 4.8 VSWR. The transceiver is implemented in a 40-nm CMOS technology, occupying 2 mm2 die area. The transceiver chip and a miniature antenna are integrated in a 3.5 × 15 mm2 area prototype wireless module. It has a receiver sensitivity of-90 dBm at 200 kbps data rate and delivers up to-25 dBm EIRP in the wireless measurement with a liquid phantom.

The gastro-intestinal (GI) tract is a very important part of the human digestive system but remains largely inaccessible for unobtrusive monitoring. Ingestible electronic devices are a very interesting concept to address this need. This paper discusses the current state of ingestible electronic devices and explores the potential they hold to provide unprecedented insight by measuring several aspects of the complex bio-chemical processes that happen in the GI tract in real-time. This will require novel sensor technology capable of measuring relevant markers with adequate specificity and accuracy. In order to be able to scale this functionality down to a form factor of an easily digestible pill, ultra-low-power wireless interface electronics are needed. This poses certain challenges and innovation opportunities related to sensing, wireless communication and powering to enable the next generation of ingestible electronic devices. [2020-0164]

An on-chip DFLL (Digitally Frequency Locked Loop) based wakeup timer with a time-domain trimming featuring an embedded temperature sensor is presented. The proposed trimming exploits the deterministic temperature characteristics of two complementary resistors and results in a fine trimming step (±1ppm), allowing a small frequency error after trimming (

Gastroscopy is a common diagnosis method for gastrointestinal (GI) diseases, but it needs to be performed in hospitals. Existing ingestible pills can collect patients' GI information over a longer period outside of a hospital, and various sensors can be incorporated to collect more information. However, ingestible pills passing through the GI system cannot make long recordings in specific places of interest. New gastroscope research focuses on the use of the biopsy channel of an insertion tube to attach the pill on a specific surface of the GI tract for some time before it detaches itself [1]. One of the most challenging parts of such “insertable” pill design is the volume constraint. The biopsy channels in gastroscopes have a diameter of ~3.5mm (at least 3x less than existing pills), and the length of the non-bendable part should be $ (10) antenna which has high sensitivity to the surrounding environment. A crystal-less transceiver is preferred because the crystal is typically the biggest off-chip component. A mm-scale radio in [3] replaces the crystal with an FBAR but requires a special manufacturing process. A mm-scale crystal-free radio in [4] presented a network-assisted timing synchronization for its Pulse-Position-Modulation(PPM)-based system. However, transceivers operating in MICS must adhere to a carrier stability better than $\pm$ 100ppm which mandates carrier synchronization for crystal-free operation, and it is especially critical for FSK/PSK transceivers that are preferred in MICS for their better channel selectivity and interference resilience. Power-oscillator topologies [5] have been widely adopted in recent mm-scale radios owing to their small size and high efficiency. However, the external coil impedance variation due to the direct contact of tissues can influence the carrier stability of the power oscillator, and the power oscillator cannot be reconfigured as an LO for FSKIPSK-based RXs.

A 40-nm CMOS wakeup timer employing a bang-bang digital-intensive frequency-locked loop for Internet-of-Things applications is presented. A self-biased $\Sigma \Delta $ digitally controlled oscillator (DCO) is locked to an RC time constant via a single-bit chopped comparator and a digital loop filter. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). Most circuitry operates at 32 $\times $ lower frequency than the DCO in order to reduce the total power consumption down to 181 nW. High frequency accuracy and a $10 \times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $ \Sigma \Delta $ modulation to improve the DCO resolution. The proposed timer achieves the best energy efficiency (0.43 pJ/cycle at 417 kHz) over prior art while keeping excellent on-par long-term stability (Allan deviation floor

A low-power impedance detection method using a hybrid transformer and its analysis are presented. A balun is reused for the hybrid transformer to achieve area-efficiency. The complex impedance detection enables faster optimization on a tunable matching network and its calibration technique increases the detection accuracy. The proposed impedance detection method fabricated in a 40-nm CMOS process consumes only 0.83 mW and demonstrates the accuracy of less than 18° and 0.1 on the Γ detection up to $\vert \Gamma _{{\rm{Ant}}}\vert $ of 0.5 in ISM2.4 GHz band. After single-step matching network tuning, PA power and RX noise figure are improved by up to 1.2 dB and 1.3 dB, respectively.

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a "variable-preconditioned LMS" calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW.

This article presents guidelines for designing the power supply blocks of RF oscillators. To preserve their spectral purity, the requirements on the noise and ripple of the supply voltage are firstly evaluated based on the oscillator supply pushing factor and the oscillator Figure-of-Merit (FOM). Those specifications are then employed to design and estimate the power efficiency of an analog low-dropout regulator (LDO) and a switched-capacitor DC-DC converter. As a proof of concept, a 2:1 or 3:2 switched-capacitor DC-DC converter is implemented and directly connected to our previously published 4.9 – 5.5 GHz LC oscillator. The converter provides a 1V supply voltage with a noise ≤ 0.9nV/ $\sqrt {Hz}$ at 1MHz and does not affect the inherent phase noise of the oscillator. The ripple amplitude of the converter is 30mV while its effect is suppressed by the spur reduction block embedded in the oscillator.

Various medical systems exist for monitoring people in daily life, but they typically require the patient to wear a device, which can create discomfort and can limit long-term use. Contactless vital-sign monitoring would be preferable, but such technology is challenging to develop as it involves weak signals that need to be accurately detected within a practical distance, while being reliably distinguished from unwanted disturbance. Here, we show that a radar-based sensor can be used to monitor the individual vital signs (heartbeat and respiration) of multiple people in a real-world setting. The contactless approach, which does not require any body parts to be worn, uses two antennas (one transmitter and one receiver) and algorithms for target tracking and rejection of random body movements. As a result, it is robust against moderate random body movements (limb movements and desk work) and can keep track of individual people during vigorous movement (such as walking and standing up). A radar-based sensor can monitor the individual vital signs—heartbeat and respiration—of multiple people in a real-world setting, keeping track of individual people during vigorous movement.

For remote vital signs and occupancy detection in many smart home/building applications, radar sensors are a preferred option over cameras, due to privacy preservation and robustness to ambient light conditions. These radars not only need to provide precise range and vital signs information over meters distance, but also preferably can operate on a battery up to a few months or even years, for cost and practical reasons (like smoke detectors). State-of-the-art remote vital-sign sensors typically use an impulse-radio UWB (IR-UWB) radar [1,2] because it provides a range resolution

A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming $\Delta \Sigma $ switched-capacitor PA (SC-PA) achieves more than $10\times $ power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power.

Duty-cycling is required to reduce the overall power consumption in IoT systems to extend the battery lifetime, which requires ultra-low-power clock generations. In this work, both the role of clocking in the whole system and the technical challenges for on-demand burst-mode operation will be discussed. In addition, an overview of state-of-the-art low-energy clock generation techniques and their performance trade-offs in terms of frequency, stability, and noise will be provided. As an example, we will show two clock generation circuits to illustrate how the challenges can be addressed.

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and $16.7~\mu \text{W}$ at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

A digital polar PA for LTE-based cellular Internet of Things (CIoT) is presented. It features a class-G back-off efficiency enhancement, using only one single supply. The PA consists of a number of parallel switched-capacitor (SC) cells. Each cell can be configured in two output-power modes, using only a single supply. At 807MHz, the peak output power is 27.1dBm, with an efficiency (PAE) of 33.3%. The efficiency at −6dBps and −12dB ps is 22.5% and 14.4% respectively, which is an improvement of 1.3x and 1.7x compared to class-B. The 13-bit resolution enables a power-control range for Cat-M1 and Cat-NB1 signals of >63dB. In that range, the EVM is

A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.

This paper presents a low-voltage (0.8V) ultra-low-power Bluetooth 5(BT5)/Bluetooth Low Energy(BLE) digitally-intensive transceiver for IoT applications. In comparison to BLE, BT5 has a 2x higher data-rate and 4x longer range, while having >8x longer packet. The BLE prior arts [1-5] have made significant efforts to minimize the power consumption for longer battery life, as well as the chip area. However, the prior-art Cartesian BLE radios consume namely 6 to 10mW [1-3] to achieve a DD ) (>1.0V). Operating a BLE RF transceiver at a lower V DD (e.g., DD down to 0.85V. However, it suffers from a degraded sensitivity due to a poor deviation frequency control and an excessive loop delay, limited ACR (Adjacent-Channel-Rejection) due to the digitally-controlled-oscillator (DCO) side-lobe energy, and an undefined initial carrier frequency due to the lack of a PLL/FLL that could have a risk of tracking to an interference. This work presents a fully-integrated 0.8V phase-domain BT5/BLE-combo transceiver, including a PHY-layer digital baseband (DBB), and addresses the above-mentioned issues by employing two key techniques: 1) a hybrid loop filter with a loop-delay compensation for DCO side-lobe suppression to enhance interference tolerance, and 2) an all-digital PLL(ADPLL)-based digital FM interface shared between RX and TX is employed, including a deviation frequency calibration, and it also precisely defines the initial frequency. Moreover, the PHY-layer DBB that supports a packet-mode phase-tracking RX operation is also demonstrated.

A WiFi (IEEE 802.11g) and BLE combo transmitter (TX) for IoT applications is presented. A wideband digital polar architecture consisting of an all-digital PLL-based frequency modulator and a switched-capacitor digitally-controlled PA achieves optimal energy efficiency for both WiFi and BLE. The dynamic FM correction and AM alias suppression techniques are applied to support 20MHz 802.11g. Implemented in 28nm CMOS technology with 0.9V supply, this highly reconfigurable TX achieves -22dB EVM for 802.11g up to MCS4 and 1.6% FSK error for BLE. The transmitter only occupies 0.65 mm2 and consumes 27mW and 15mW with OdBm output power for WiFi and BLE, respectively. It results in an excellent energy efficiency of 0.62nJ/b. © 2018 IEEE.

This work presents a fully-integrated sub-GHz radio System on Chip (SoC) for Low-Power Wide-Area Networks (LPWAN) and Internet of Things (IoT) applications. The receiver (RX) achieves 77dB blocker rejection and -106dBm sensitivity at 50kbps. The transmitter (TX) features a Switched-Capacitor Power Amplifier (SCPA) that delivers 13.5dBm output power. To fulfil stringent Japanese emission regulation, a novel digitally time-dithered SCPA ramping technique is proposed. The presented RX and TX consume 8mW and 113mW, respectively, from a supply as low as 1.2V.

This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular IoT wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired with a standard-compliant transmitter, the proposed wakeup receiver method minimizes the overhead in system power, area and complexity. The proposed 2-dimensional wakeup pattern reduces the latency of a wakeup event to below 100μs. Supplied at a battery voltage of 2V, the chip fully integrates a power management unit, a wakeup receiver with offset and noise suppression, a low power digital baseband with automatic gain control and RSSI estimation, and a crystal oscillator. With a BLE compliant signal, the chip achieves -58dBm sensitivity, and a >600s mean time without false alarm, consuming 195μA.

An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this receiver achieves -104dBm sensitivity in the 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils the adjacent channel rejection requirements with at least 17dB margin. The digital polar transmitter achieves -31dB EVM and 10dB spectral mask margin.

A Digital IF Phase-Tracking Doppler radar is presented for accurate displacement measurements and vital signs monitoring. This novel architecture implements a digital Phase-Locked-Loop (PLL) in phase demodulator configuration to extract the phase modulation caused by a moving target without requiring the small-angle approximation condition and solving the null-point issue. This facilitates the accurate measurement of a target's motion. Experimental results successfully demonstrated the feasibility of the proposed approach.

Wearable/implantable devices, e.g., heart-rate-monitor straps and implanted wireless sensors, need to be ultra-low-power (ULP), compact, and also robust against the proximity effect, which can significantly degrade the antenna and front-end performance and hence battery lifetime. A fully integrated adaptive front-end with a tunable matching network (TMN) using low-power and fast impedance detection is highly desirable for robust and efficient operation.

The Internet-of-Things (IoT) is gaining momentum, and the ultra-low-power (ULP) RF transceiver is one of the key enablers. Generation of the local oscillator (LO) consumes a significant share of the total energy of these ULP transceivers which are typically powered by small batteries. Therefore, a fractional-N PLL needs to perform LO frequency synthesis and modulation with a very stringent power budget, i.e., below 1mW [1]. A digital PLL is favored in these applications because of the benefit of small area, which is also a critical cost consideration in IoT. On the other hand, the LO quality generated by these ULP PLLs cannot be compromised, and it needs to fulfil the RF requirements defined in the IoT standards, e.g., Bluetooth Low Energy (BLE). Although the integrated phase error is less stringent in IoT standards, the spectral purity requirements remain critical in order to fulfill the regional spectrum regulations, e.g., FCC. A high fractional spur level due to the non-linearity in PLLs (e.g., from a TDC) introduces the unwanted emission. In this work, we present a ULP dividerless digital PLL with a power-efficient spur-mitigation technique. Furthermore, one of the critical issues of the dividerless (or sub-sampling) PLLs, the lack of frequency capture capability without the assistance of an extra power-hungry frequency-locked-loop (FLL), is addressed and mitigated by the proposed digital phase unwrap technique.

We propose an ultra-low-power (ULP) and low-voltage phase-tracking RX for IoT applications. Several popular standards are defined for IoT, e.g., IEEE802.15.4 and Bluetooth Low Energy (BLE), where they envision massive numbers of interconnected sensors; however, the cost of replacing/recharging batteries can become an impediment to their massive deployment. In this work, aggressively improving the transceiver energy efficiency, lowering the supply, and simultaneously reducing the cost (die area) of the design are our primary goals. Hence, we propose a digitally-controlled oscillator (DCO)-based phase-tracking RX, which efficiently combines frequency downconversion, channel selection, carrier generation and signal demodulation, all of which lead to an ultra-low-power, low-voltage and low-cost RX.

Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (T s ) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of T s of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).

This paper presents an ultra-low-power (ULP) 2.4GHz RX for short-range wireless personal and body-area networks. In such applications, the RF transceiver consumes up to 90% of the total battery energy in a remote sensor node. In order to extend the operation lifetime, it is a primary design goal for such transceivers to improve the energy efficiency, expressed as power consumption/data-rate, to below 1nJ/bit. Although energy-detection or superregenerative ASK RXs [1] are very efficient, they are vulnerable to interference and this leads to a poor quality of the wireless link in a crowded 2.4GHz ISM band. On the other hand, FSK/PSK-type modulations are popular in the target applications because of their power-efficient hardware and higher immunity to interference. They are also widely adopted in many short-range wireless standards like IEEE802.15.4 and Bluetooth Smart. Thanks to the constant-envelope nature of FSK/PSK-type modulations, e.g., HS-OQPSK, they only modulate data on the carrier frequency or phase, so the TX hardware can be simplified, while the efficiency can be enhanced by driving the circuits into a saturated mode, e.g., PLL-based FSK TXs [2,5]. Similarly, in the RX counterpart, instead of processing the signal in the I/Q domain, it can be demodulated in the phase domain by using a phase-ADC [3]. However, such approach still requires a power-hungry high-frequency multi-phase LO generation and “2-dimensional” downconversion and filtering circuits. In the single-channel RX of [4], the VCO is part of the carrier-recovery and phase-demodulation loop. Therefore, the VCO frequency can be easily “pulled away” by an interferer, and the RX has a poor sensitivity because phase noise is deteriorated by the signal chain when input level is low.

This paper presents a 400-MHz energy-efficient Medical Micro-power Networks transmitter for neural-muscular signal sensing and stimulation applications. The transmitter can fulfill the transmission requirements defined in the MedRadio band, including the recently added 413-MHz to 457-MHz channels. The half-sine shaped offset-QPSK modulation is adopted to meet the transmission mask requirement while supporting a maximum data rate of 4 Mbps within the 6-MHz channel bandwidth. The signal modulation is performed by the proposed FIR-embedded phase modulator which employs a phase-domain FIR filter to suppress the unwanted side-lobe energy. Fabricated in a 0.18-μm CMOS process, the presented transmitter consumes only 2.6 mW from a 1-V supply, resulting in an energy efficiency of 650 pJ/bit. The measured error vector magnitude is 2.5%.

A 2.4GHz transceiver SoC, operating at minimum 0.9V, is presented as a power-efficient and cost-effective solution for the coming Internet of Things (IoT) platform. The transceiver is compliant with Bluetooth Low Energy (BLE) 4.0/4.2/5.0 PHY and 802.15.4 standards. The measured sensitivity is −93dBm at 1V, and TX output power is 1dBm. Direct battery attachment is feasible, due to the 1.5µW deep-sleep power which enables µW-range average power consumption without Low Drop-Out (LDO) regulator. The radio is fabricated in 40nm CMOS technology.

This article discusses the radio system requirements and design trade-offs of a low-power 2.3/2.4 GHz IEEE 802.15.6-narrowband transmitter for body area network applications. The IEEE 802.15.6 narrowband PHY adopts nonconstant envelope DPSK modulations. Transmitter architecture selection is a major challenge because it needs to provide both amplitude and phase modulation, with good efficiency and strict requirements on modulation accuracy and linearity for non-constant envelope modulations. A PLL-based polar transmitter with a Sigma-Delta digitally controlled power amplifier (ΣΔ-DPA) is employed for its excellent energy efficiency. Finally, this article discusses the circuit design considerations and implementation results. With balance between analog and digital implementation, and careful planning of the radio system, the polar transmitter presented in this article can meet all of the specifications defined in IEEE 802.15.6 with abundant margin, while having extremely low power consumption of 5.4 mW and excellent energy efficiency of 5.4 nJ/bit.

This paper presents a delta-sigma pulse-width digitizer (ΔΣ-PWD) architecture designed for a super-regenerative receiver (SR-RX) operated at the 400-MHz Medical Implantable Communications Service (MICS) band. The ΔΣ-PWD employs the operation principle of a ΔΣ modulator to convert the pulse-width (PW) value into digital domain and achieve fine resolution, which allows the SR-RX to support the 2-ASK/4-ASK modulations. It can be considered as the PW domain counterpart of a conventional ΔΣ modulator. The proposed architecture is capable of suppressing the PW quantization error over the direct-sampling-type PW detector by 23 dB. A linear model for the ΔΣ-PWD is devised in this paper for system analysis and design optimization. Fabricated in a 0.18-μm CMOS process, the whole receiver draws 700 μA from a 1.3-V supply, while the ΔΣ-PWD consumes only 100 μA. When operated on the 4-ASK modulation signal with 312-kbps data rate, the receiver achieves an energy efficiency of 2.9 nj/bit and -76-dBm sensitivity.

This paper presents a 400-MHz energy-efficient offset quadrature phase-shift keying (O-QPSK) transmitter for implantable multichannel neural recording applications. Transmitters for these applications must operate at low power while delivering a high data rate. The proposed transmitter incorporates a phase MUX, which directly implements the phase-shift keying operation. The O-QPSK modulation signal is generated by selecting one of the four quadrature phases based on the baseband data via the phase MUX. The power amplifier adopts the inverter-type topology for it is compatible with the quasi-constant-envelope nature of the O-QPSK signal. Implemented in a 0.18- mum CMOS process, the whole transmitter dissipates 2.9 mA from a 1.2-V supply. With a maximum data rate of 17.5 Mb/s, the proposed transmitter achieves an energy efficiency of 200 pJ/bit and is capable of delivering an output power up to -8 dBm.

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed sigma-delta modulated phase rotator (??-PR). By properly combining the multi-phase signals from the PLL output, the ??-PR effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed ??-PR adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the ??-PR on the TX output noise is also analyzed in this paper. The proposed TX with the ??-PR is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 ?m CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of -11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.

This paper proposes a novel charge pump (CP) circuit and a gated-offset linearization technique to improve the performance of a delta-sigma (??) fractional-N PLL. The proposed CP circuit achieves good up/down current matching, while the proposed linearization method enables the PFD/CP system to operate at an improved linear region. The proposed techniques are demonstrated in the design of a 2.4-GHz ?? fractional-N PLL. The experimental results show these techniques considerably improve the in-band phase noise and fractional spurs. In addition, the proposed gated-offset CP topology further lowers the reference spurs by more than 8 dB over the conventional fixed-offset approach. This chip is implemented in the TSMC 0.18-?m CMOS process. The fully-integrated ?? fractional-N PLL dissipates 22 mW from a 1.8-V supply voltage.

This paper presents an ultra-low-power (ULP) IEEE 802.11ah fully-digital polar transmitter (TX). IEEE 802.11ah is a new Wi-Fi protocol optimized for Internet-of-Everything (IoE) applications. Compared to other IoE standards like Bluetooth or ZigBee, its sub-GHz carrier frequency and mandatory modes with 1MHz/2MHz channel bandwidths allow devices to operate in a longer range with scalable data-rates from 150kb/s to 2.1Mb/s. Moreover, the use of OFDM improves link robustness against fading, especially in urban environments, and achieves a higher spectral efficiency. The key design challenges of an IEEE 802.11ah TX for IoE applications are to meet the tight spectral mask and error-vector-magnitude (EVM) requirements as for conventional Wi-Fi standards (e.g., 802.11n/g), while achieving low power consumption required by IoE applications. The presented TX applies a fully-digital polar architecture with a 1V supply, and it achieves more than 10× power reduction compared to the state-of-the-art OFDM transceivers [1–4]. Without any complicated PA pre-distortion techniques as in [5], it passes all the PHY requirements of the mandatory modes in IEEE 802.11ah with 4.4% EVM, while consuming 7.1mW with 0dBm output power.

This paper presents an ultra-low power 2.4 GHz FSK/PSK RX for wireless personal/body area networks. An energy-efficient single-channel phase-domain receivers based on a sliding-IF phase-to-digital conversion (SIF-PDC) loop is presented. It equivalently transforms the signal processing from analog I/Q domain to the digital phase domain, which save almost 40 % power consumption. A phase rotator is employed in the phase-tracking loop to decouple the carrier generation and frequency demodulation, which guarantees the frequency stability and enables wideband operation. The analog multiplier and the single-bit quantization implementation improves the interference rejection. Fabricated in a 90 nm CMOS technology, the presented RX consumes 2.4 mW at 2 Mbps data rate, i.e., 1.2 nJ/b efficiency, and achieves a sensitivity of −92 dBm.

ESSCIRC 2015 - 41st IEEE European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14-18 September 2015

An energy-efficient, flexible radio SoC with RF front-end (RFFE), digital baseband (DBB) and microcontroller (MCU) for medical/healthcare applications in 315/400 MHz bands is presented. The SoC is fully-compliant with the IEEE 802.15.6 standard in 400MHz bands, and also supports proprietary modes, including high data rate (HDR) modes with x2/4/8 data rates (max 3.6Mb/s) to support applications like EEG, and low-power modes with 1/16 data rate to minimize sensor node power consumption. The total power consumption of 3.5mW (RX, 3.6Mb/s, -77dBm sensitivity) enables best-in-class power efficiency of 1nJ/bit.

In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where −95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.