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An important figure of merit in microwave superconducting quantum interference device multiplexer (MW-MUX) is the quality factor of superconducting resonators. In advanced industrial science and technology (AIST), the intrinsic quality factor ${\boldsymbol{Q}_{{\mathbf i}}}$ of the resonators in the MW-MUX chips degraded significantly compared to those in the resonator-only chips owing to something during the fabrication process. In this study, we have investigated the damage process by conducting controlled experiments and an SEM-EDX analysis. As a result, we have confirmed that the metallic layers (Pd and Nb) were not removed completely and remained along the edge of the resonator, which resulted in the degradation of ${\boldsymbol{Q}_{{\mathbf i}}}$ . Further, we have invented a new process to overcome this imperfection during the removal of Pd layer using so called “caldera planarization”. The metal line that remained along the edge was not observed in the MW-MUX chips fabricated using this improved process. Finally, we have achieved ${\boldsymbol{Q}_{{\mathbf i}}}$ as high as that of resonator-only chips using the improved process.

We are developing an x-ray imaging spectrometer for Super DIOS satellite mission, a future x-ray observatory, planned by JAXA, to be launched in 2030’s. Super DIOS will reveal the nature of the missing baryon in the warm-hot intergalactic medium because of its fine energy and angular resolution, large effective area and large field of view. A main detector on-board Super DIOS consists of a transition-edge sensor (TES) microcalorimeter array of over 30,000 pixels working at a temperature below 100 mK and it poses a considerable technical difficulty to the readout. A microwave superconducting quantum interference device (SQUID) multiplexing is promising technique and expected to achieve a large scale readout of more than 30,000 pixels. We describe our development of a 40-channel microwave SQUID multiplexer with low-noise characteristics∗ and a demonstration of simultaneously reading out 40-pixel TESs. Finally, we discuss a future prospect and a feasibility of reading out an array of more than 30,000 pixels.

In order to read out current signals from large-scale arrays of transition edge sensors (TES), microwave SQUID multiplexers (MW-MUX) have been developed by several groups. Reduction of crosstalk induced in the multiplexer is important in order to maintain the energy resolution or the noise equivalent power of detector arrays. In the present study, crosstalk between channels in MW-MUX with five different designs is experimentally evaluated. The resonance frequency separation is ten times as large as the resonator bandwidth. Without flux-ramp modulation, crosstalk between two adjacent channels neighboring in position decreases to ≍1 × 10–3 with increasing resonance frequency separation to ≍100 MHz. Crosstalk between SQUID channels neighboring in resonance frequency also decreases to 4 × 10–3 with increasing the distance to 2.5 mm. We show that nonlinear error can occur due to the crosstalk with flux-ramp modulation. Flux readings from a well-designed multiplexer exhibit crosstalk of less than 1 mΦ0 peak-to-peak and nonlinear errors of less than 2 mΦ0 peak-to-peak, which is sufficient for the readout of the gamma-ray TES arrays being developed. These results can provide guidelines for suppressing both the crosstalk and the nonlinear error to less than the criterion of TES spectrometers with typical energy-resolving ability.

著者人数: 14名, Accepted: 2016-02-17, 資料番号: SA1150322000

Accepted: 2016-02-17, 資料番号: SA1150323000

We report very-low-noise, fast-response, middle-scale multiplexing in a microwave superconducting quantum interference device multiplexer (MW-Mux) as a transition-edge sensor (TES) readout. Our MW-Mux is able to read 40 channels with 500 kHz sampling and has a low readout noise of 0.9 μ Φ 0 / Hz (where Φ 0 is the magnetic flux quantum), equivalent to 9 pA / Hz. By contrast, a multiplexer of less than 10 pixels with 500 kHz sampling and ∼ 2 μ Φ 0 / Hz readout noise has so far been reported in the literature. Owing to the 500 kHz sampling, our MW-Mux exhibits a fast response to detect a TES pulse with a rise time around 12 μ s. We demonstrated simultaneous readout of 38 pixels from an array of x-ray TES microcalorimeters. The measured full-width values at half-maximum spectral resolution ranged from 2.79 to 4.56 eV, with a median value of 3.30 eV at 5.9 keV, including a ∼ 10 % contribution of readout noise, i.e., 0.9–1.7 eV.

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm 2 process based on conventional Nb/AlO x /Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

Accepted: 2013-12-17, 資料番号: SA1004633000

We have fabricated three-dimensional double-layer strip arrays of Nb and observed flux penetrations into these strip arrays with applied field perpendicular to the plane by using the magneto-optical imaging method. In strip arrays with large overlaps between strips we observed flux avalanches even at 1.5 K below the critical temperature. Novel flux avalanches showed up as one-dimensional penetrations perpendicular to the strip arrays in samples with the maximum overlap. Enhanced demagnetization effect and thermal conductivity between the top and bottom layers are believed to cause these avalanches.

Accepted: 2017-05-02, 資料番号: SA1170002000

A cryogenic current comparator (CCC) is an instrument of great importance in electrical metrology, which provides a ratio of two currents with ultimate accuracy based on superconductivity. It is used for dc resistance calibration in many national metrology institutes. Conventional CCCs consist of multi-turn coils of wire windings, a multi-layered shield of superconductor foils and a separate SQUID sensor. This implementation results in a bulky device too massive to cool with a mechanical cryocooler, making a system inconvenient. A new implementation of CCC, an integrated CCC (ICCC) consisting of thin-film spiral coils, a thin-film superconducting shield and a SQUID sensor integrated on a single chip, enables a user-friendly system operated with a compact cryocooler. Prototype ICCC chips were designed and fabricated by using a superconducting Nb integrated circuit technology with chemical-mechanical polishing. The basic operation of the prototype ICCCs was confirmed by monitoring periodic flux-voltage characteristics of the SQUIDs.

We have estimated jitter accumulated in data and clock lines of an SFQ Reconfigurable Data Paths processor and its impact on the operating frequency and identified critical components. In order to prevent performance degradation, we have proposed to divide the processor in several parts clocked separately by an external jitter-free system clock. FIFO buffers and clock controllers inserted between the processor stages are used to synchronize each stage with the next one and as a result the accumulation of jitter is limited to one stage of the processor only. Two versions of a synchronization scheme prototype have been designed for both ISTEC-SRL standard 2.5 kA/cm2 and advanced 10 kA/cm2 processes and successfully tested at high speed.

A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm 2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5 kA/cm 2 to 10 kA/cm 2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400 GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100 GHz.

We investigated the most suitable device structure for large-scale SFQ circuits and propose a new Nb 10-layer device structure that is composed of active layers including junctions at the top, PTL layers in the middle and DC power layers at the bottom. This device structure enables us to reduce the influence of the magnetic field due to large bias currents and to form a Nb/AlOx/Nb junction layer in the last part of the fabrication sequence. To achieve this structure, we developed a higher quality planarization that could remove the residual slight roughness after standard caldera planarization. We fabricated a diagnostic chip that is composed of test elements such as junctions, contacts, resistors and many kinds of process test patterns. We obtained sufficient characteristics for the diagnostic chips. Moreover, to evaluate the fabrication process, we designed and fabricated several shift registers. We confirmed the correct operation of an up to 2560-bit shift register having 10,281 junctions.

We are developing a large-scale reconfigurable data path (LSRDP) using single-flux-quantum (SFQ) circuits as a fundamental technology that can overcome the power-consumption and memory-wall problems in CMOS microprocessors in future high-end computing systems. An SFQ LSRDP is composed of several thousands of SFQ floating-point units connected by reconfigurable SFQ network switches to achieve high performance with low power consumption. In this study, we designed and implemented an SFQ floating-point multiplier (FPM), which is one of the key components of the SFQ LSRDP. We designed a systolic-array bit-serial half-precision FPM using the 2.5 kA/cm2 Nb process. The resultant circuit area and number of Josephson junctions are 6.22 mm times 3.78 mm and 11044, respectively. The designed clock frequency is 25 GHz. We tested the circuit and confirmed the correct operation of the FPM by on-chip high-speed tests.

We have developed an advanced process for fabricating a next-generation multi-layer Nb integrated circuit structure incorporating a top active layer. In this structure, the passive-transmission-line (PTL) layer is placed between the top active layer and a DC-bias current layer at the bottom. This structure will make it possible to flexibly design active circuits and PTL wiring, and will also enable active circuits to be effectively shielded from magnetic fields generated by a large DC-bias current. Both the DC-bias current layer and the PTL layer are planarized; however, the top active layer is fabricated without planarization. To fabricate this new structure, it was necessary to achieve a better planarization process for junctions formed over underlying Nb patterns. The combined process we developed comprising additional SiO2 deposition and additional mechanical polishing after the standard Caldera planarization process results in superior planarization for junction formation. We obtained excellent characteristics of junctions formed over underlying pattern edges when they were fabricated on surfaces planarized using this new process. Using the process, we fabricated new 10-Nb-layer integrated circuit structures and estimated the characteristics of their circuit elements.

We have studied single-flux-quantum (SFQ) propagation properties in passive transmission lines (PTLs) based on a 10-Nb-layer device structure (ADP2). In ADP2, we can use the PTLs with a line width about 5 mum, one seventh of conventional line width by adopting a strip line (SL) structure and increasing the characteristic impedance. The evaluation has been conducted on the PTL length and the via-hole structure by using ring oscillators. We found that the decrease in the operating region was larger for longer PTL, compared with that in a conventional device structure (STD2). The results would be caused by the increase in the surface resistance. The via-holes connecting the PTLs on different layers have more complicated structure than those of STD2. We have designed the via-hole structure using the electromagnetic wave simulator HFSS. As a result, we have demonstrated sufficiently large operating margins at any data rates up to 80 Gb/s even for the ring oscillator with 30 via-holes.

We have evaluated the effects of a DC power (DCP) layer in a 10-Nb-layer device using SQUIDs and large-scale Josephson transmission lines (LS-JTLs). The 10-Nb-layer device has recently been developed for SFQ LSIs, with an active layer including Josephson junctions (JJs) at the top, two passive transmission line layers in the middle, and the DCP layer for bias current feeds at the bottom. The evaluation with SQUIDs revealed that the 10-Nb-layer device structure drastically reduced the magnetic flux induced by DC currents flowing through the DCP line, in comparison with the previous advanced process device structure. A major factor for this reduction was an increase in the number of ground layers between the DCP layer and the active layer. In the test of the LS-JTLs containing about 12000 JJs, we obtained the operating margins as wide as numerically simulated ones. We also observed no difference in the margins between a method for extracting ground return currents through ground layers and that through the dedicated layer. These results demonstrated that the 10-Nb-layer device structure is suitable for SFQ-LSIs.

We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In this paper, we designed and implemented an SFQ half-precision FPA and carried out on-chip high-speed tests. The data format of the half-precision FPA obeys the IEEE standard, in which two input data streams, an 11-bit significand and a 6-bit sign/exponent, are processed bit-serially. The floating-point addition is performed by three steps: (1) alignment and rounding of significands, (2) addition/subtraction of the significands, and (3) normalization of the result. We implemented an SFQ half-precision FPA using the SRL 2.5 kA/cm2 niobium standard process. The size, power consumption and total junction number are 5.86 mm times 5.72 mm, 3.5 mW and 10224, respectively. The simulated DC bias margin is plusmn20% at 20 GHz operation, which corresponds to the performance of 1 GFLOPS. We successfully confirmed the correct operation of the FPA except a read-out circuit for the significand at 24 GHz by on-chip high-speed tests.

We developed an Nb-based fabrication process for single flux quantum (SFQ) circuits in a Japanese government project that began in September 2002 and ended in March 2007. Our conventional process, called the Standard Process (SDP), was improved by overhauling all the process steps and routine process checks for all wafers. Wafer yield with the improved SDP dramatically increased from 50% to over 90%. We also developed a new fabrication process for SFQ circuits, called the Advanced Process (ADP). The specifications for ADP are nine planarized Nb layers, a minimum Josephson junction (JJ) size of 1×1μm, a line width of 0.8μm, a JJ critical current density of 10kA/cm2, a 2.4Ω Mo sheet resistance, and vertically stacked superconductive contact holes. We fabricated an eight-bit SFQ shift register, a one million SQUID array and a 16-kbit RAM by using the ADP. The shift register was operated up to 120GHz and no short or open circuits were detected in the one million SQUID array. We confirmed correct memory operations by the 16-kbit RAM and a 5.7 times greater integration level compared to that possible with the SDP.

We have investigated the effect of a dc-power (DCP) layer on the performance of single flux quantum (SFQ) circuits by changing the film thickness of a ground plane (GP). The DCP layer was placed below the GP and was used as bias current feeds. Two measurements were conducted. One was direct detection of the magnetic flux above the GP by using SQUIDs. The results indicated that the GPs with film thicknesses of more than 400 nm were effective to completely suppress the flux under the condition that the return current was extracted from the ground plane. The other was evaluation of the operating margins of the 408 bit shift register circuits (SRs) with 8032 Josephson junctions and a total designed bias current of 1.05 A. The results showed that a 500 nm thick GP had an advantage over a 300 nm thick GP in the dependence of the upper margin on the bias current port of the SR.

We have developed an advanced fabrication process for fabricating Nb integrated circuits with up to nine planarized Nb layers, and with critical current density of Josephson junctions of 10 kA/cm2. We have continued to improve this advanced process. For nine-layer integration, we readjusted film thickness of Nb and SiO2 layers in order to reduce the strain of films and substrate. Total film thickness of the nine-Nb layered structure was about 3 mum; this was kept nearly as thin as that of the six-Nb-layered structure. The resulting thinner SiO2 layers enabled narrower passive transmission line wiring, which had the advantage of smaller occupation area. The room temperature measurement of process monitoring patterns is useful for screening defective wafers in the middle step of the process. For higher circuit reliability, we modified fabrication processes such as junction planarization. As a result, the reliability of SiO2 insulation between an upper and a lower Nb wire adjacent to a Josephson junction was improved.

To achieve larger scale and higher speed single flux quantum (SFQ) circuits, we have been developing a 10-kA/cm2 Nb multi-layer fabrication process composed of more than six pla- narized Nb layers, an Nb/AlOx /Nb junction layer, a Mo resistor layer, and SiO2 insulator layers. To evaluate reliability of the fabrication process, we have designed superconducting random access memories (RAMs) with four different memory capacities: 256, IK, 4 K, and 16 K bits. Although the circuit configuration of these RAMs is almost the same as that of previously developed ones that have conventional latching devices, we modified the circuit parameters and layout design based on specifications of the new fabrication process. We have obtained operations for the 256-bit RAM with a bit yield of 100%, the lK-bit RAM with a bit yield of 99.8%, and the 4K-bit RAM with a bit yield of 96.7%. The number of defects in the 4K-bit RAM was estimated to be approximately 10. We confirmed that evaluations using the RAMs were effective at detecting defects due to the fabrication process.

Large-scale SFQ integrated circuits require a large amount of dc-bias current. The magnetic fields induced by the dc-bias currents and the return currents flowing in a ground plane have a great influence on the performance of SFQ circuits. As an approach to reduce the influence, the dc-power (DCP) layer placed under a ground plane is newly introduced in SRL advanced Nb process. We have experimentally evaluated the effects of the DCP layer using SQUIDs and large-scale Josephson transmission line (JTL) circuits with more than 10,000 junctions. The SQUIDs showed that there was small magnetic flux coupling between the DCP lines and themselves and that the coupled flux was enhanced by the return current. The coupled flux decreased with increasing line width of the DCP lines and with increasing distance from the centerlines of them. In the large-scale JTL tests, the cells with DCP patterns showed wider operating margins than the CONNECT OPEN cells with partial magnetic shielding of bias current lines. The test results also showed that a line shape along the periphery of a cell was more effective than a plane shape within a cell as a DCP layer pattern for bias current feeds.

We report random access memories (RAMs) based on vortex transitional (VT) memory cell developed with the newly developed AIST 10-kA/cm², Nb 4-layer fabrication process, called High-Speed Standard Process (HSTP). We obtained more effective mutual coupling structure by fully use of all the wiring layer, and successfully reduced the cell size to 25 μm square, which indicated roughly 50% increase in density compared to the previous design. We reduced the critical currents of Josephson junctions and load resistance to be matched with driving circuitry. We tested the miniaturized VT memory cell, and obtained a sufficient margin width of ~15%, and also confirmed correct operations of the other components, including a latching driver and address decoder.

Submicron Nb/AlOx/Nb junctions having high critical current density of more than 20 kA/cm2 are required for realizing single-flux-quantum (SFQ) circuits operating at a high speed of more than 100 GHz. We have developed a 20 kA/cm2 process having submicron circular junctions. 1000-serially-connected circular shape junctions having six different diameters of 0.5 μm, 0.564 μm, 0.7 μm, 0.9 μm, 1.1 μm, and 1.3 μm have been designed. The 0.564 μm junction is designed to be 50 μA with critical current density of 20 kA/cm2, which is a minimum current value of a target SFQ circuit design. We totally fabricated 12 wafers with the 20 kA/cm2 process. The 1σ spread of critical currents (Ic) depending on junction sizes and the run-to-run reproducibility of critical current densities are reported as a summary of these fabrications. We obtained Ic scattering of 1σ≤ 2% even in the minimum circular junction of 0.25 μm2 in several fabrication runs.

We are developing low-power dc-SQUIDs to read out TES X-ray microcalorimeter arrays with frequency-division multiplexing (FDM) towards future X-ray satellite missions. In future space missions, large-format TES X-ray microcalorimeter arrays with hundreds to thousands of pixels are promising detectors achieving high energy resolution and high spatial resolution at the same time. To read out such a large-format array with a limited cooling power at the cryogenic stage, TES pixels are multiplexed in the frequency domain and read out using SQUIDs with small heat dissipations. We are developing low-powered dc-SQUIDs with an adequate gain and a low noise characteristic for TES FDM readouts. With these features, the SQUID can suffice to be the only amplifier in the cold electronics even though it can be placed at the cryogenic stage below 100 mK, enabling a simple single-staged cryogenic configuration. Using the low-power SQUID, we are developing multi-input SQUID chips with built-in bandpass filters used for the channel separation in FDM. Within the size of 2.5×2.5 mm, it carries the low-power SQUID, a TES shunt resistor, and LC bandpass filters for four channels. We are also developing a same-size extension chip that consists of the bandpass filters for four other channels, and it can be attached to the multi-input SQUID chip with only two bonding wires. With these chips, the cryogenic stage setup is drastically simplified. The designs and experimental results of the SQUIDs will be discussed.

We have evaluated the inductances of the striplines and the stacked vias which are realized in the planarized 6-Nb-layer device fabricated by our advanced Nb fabrication process. The inductances of centered and off-center striplines were compared with inductances of the microstrip lines which had insulators with the same thicknesses as an insulator or a thinner insulator between the signal line and the ground plane in the stripline. The centered striplines showed the sheet inductances about 0.65 times as much as those of the microstrip lines. The factor would be useful for designing passive transmission lines (PTLs) based on the stripline, and would provide the estimate of the line width of the PTLs. The stacked vias showed a small increase of ∼0.1 pH in inductance every additional a via stacked on top of a via. A comparison between the inductance of the stacked via and that of conventional vias revealed that the stacked vias are effective in reduction of layout areas and parasitic inductances.

We developed a fabrication process for planarized multi-layer Nb SFQ circuits. This new process has several new steps for achieving a planarized multi-layer structure with a high critical current density. We have so far fabricated about 30 wafers, and we have measured the characteristics of Josephson junctions in multi-layer structures. We confirmed small spreads and high reproducibility in the critical current, and we also achieved a high junction yield. In contrast, we detected a minor degradation of the gap voltage, which had no serious influence on circuit operation. Based on the measured results, we believe that planarization was the most probable cause for this degradation.

Designs and test results for a single-flux-quantum (SFQ) eight-bit shift register circuit operating at frequencies above 100 GHz are described. The high-speed performance was realized by introducing a planarized 10 kA cm−2 Nb fabrication process as an advanced process and by adopting middle-damped junctions with McCumber parameters βc of 1.8–2.9 in the circuit. The middle-damped junctions were used to reduce the repulsion between SFQ pulses and to adjust the timing. The circuit was designed using a cell-based design method and was tested by constructing an on-chip test system with a ladder-type four-bit high-frequency clock generator. We confirmed its correct operations up to 120 GHz.

We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.

The Superconductivity Research Laboratory has successfully fabricated large quantities of single flux quantum (SFQ) large scale integrated circuits, including several thousands of Josephson junctions (JJs). Using a Jc = 2.5 kA cm−2 process in which the number of Nb layers was four and the minimum JJ size was 2 µm square. We developed a new advanced fabrication process that produced a Jc = 10 kA cm−2, nine Nb layers and a minimum JJ size of 1 µm square. The increase in the number of Nb layers was achieved by using a planarization technique. The target of our next generation process is a Jc = 40 kA cm−2 with a 0.5 µm square for the minimum junction size. This specification will be achieved by using advanced semiconductor technologies. This process will enable SFQ circuits to be produced with one million JJs on a chip and achieve a clock frequency greater than 100 GHz.

We developed a 10 kA/cm 2 Nb fabrication process, whose device structure was composed of six planarized Nb-layers, an Nb/AlO x /Nb junction layer, an Mo resistor layer, and SiO 2 insulator layers to make larger scale, higher speed single-flux-quantum (SFQ) circuits that have more than 100 k junctions.It is very important to evaluate the process reliability in relation to the uniformity of the device parameters and the defect rate of the fabrication process. To evaluate the process reliability, we designed and tested many kinds of process test circuits, including 100 k junctions and 60-k serially connected contacts. We obtained excellent insulation properties, even in the six-Nb-layer structure. The standard deviations of the critical currents for 2000 1.2-μm-square junctions were less than 1.9%. We obtained a critical current of more than 8 mA, even for the 60-k serially connected contacts. Based on these results, we obtained sufficient reliability to realize the SFQ circuits including more than 100 k junctions.

Series Nb/AlO x /Nb junction array circuits are commonly used for evaluation of a critical current ( I c ) spread as an important parameter on Nb-based LSI chips. We present a junction array circuit suitable for accurate evaluation of the spread. The circuit has a tolerance for the I c suppression caused by external noises and synchronous switching which are often observed in measurements. Key elements of the circuit are the low value resistors, large value capacitors, and high value resistors inserted between wires and chip bonding pads. This paper describes effects of these key elements on current–voltage characteristics of junction arrays.

The via-wiring process for niobium large-scale single-flux-quantum (SFQ) circuits was studied from two viewpoints: niobium deposition and inter-level-dielectric (ILD) SiO 2 deposition. It was found that superconductive critical current density ( J c ) strongly depends on the target-to-wafer distance (TS) during niobium deposition. Transmission-electron-microscope observation revealed that the niobium film sputtered under a long-TS condition has enough step coverage, but less crystallinity and lower density. Moreover, deposition at a lower incident angle at the via walls was found to cause the degradation. Grain growth at an inclined crystal orientation during the deposition is thought to produce high porosity in the film, resulting in poor superconductive characteristics. Vias formed in the SiO 2 deposited without substrate biasing were also found to degrade niobium film crystallinity. The most probable cause of this niobium degradation is the influence from water (moisture) absorbed in the SiO 2 vias. These results show that reliable vias can be fabricated by niobium sputtering with optimized TS and by SiO 2 formation with substrate biasing.

To improve the operating speed and density of Nb single-flux-quantum integrated circuits, we developed an advanced fabrication process based on NEC's standard process. We fabricated planarized six-Nb-layer circuit structures using this advanced process. This new structure has four Nb wiring layers for greater design flexibility. To shield the magnetic field produced by the DC bias current, the DC bias power supply layer was placed under the groundplane. The critical current density of the Josephson junction was 10 kA/cm/sup 2/. We fabricated and tested more than 10 wafers and demonstrated that the six-layer circuits were successfully planarized. We also confirmed insulation between each Nb layer and the reliability of superconducting contacts. This planarization did not significantly degrade the junction characteristics. We measured small spreads in the critical current of less than 2%. These results demonstrated the effectiveness of this advanced process based on mechanical-polishing planarization.

The authors evaluated the effect of photomask pattern shape for a counter-electrode on critical current I/sub c/ uniformity and controllability in Nb/AlOx/Nb junctions. Circular, square, and 2 kinds of optical proximity correction (OPC) square patterns were used as the mask pattern shape. Although there was no difference in the I/sub c/ uniformity between square and OPC junctions, the OPC junctions exhibited smaller shrinkage in junction size than the square junction. In addition, the OPC junctions improved the chip-to-chip variation in the shrinkage. The circular junction exhibited the smallest variation in the shrinkage, and had an advantage in I/sub c/ uniformity for smaller than 1.0 /spl mu/m/sup 2/ junctions in comparison with the other junctions. The shrinkage of the circular junction was the largest of all the junctions. This paper describes the recommended choice of the photomask pattern shape for several Nb LSI technologies.

We developed a method of planarization that can be used to fabricate large-scale single-flux-quantum (SFQ) circuits with more than 100-k junctions. Most conventional planarization methods have problems with being able to obtain sufficient planarity in devices with Nb wiring having various pattern sizes and area densities ( pattern dependence problem ). We eliminate this pattern dependence problem directly by removing the convex areas of SiO 2 insulator layer covering Nb wiring layer using the Nb wiring pattern array information. The practical process involves the combination of three steps to form the SiO 2 insulator layer, i.e., (1) bias-sputtering, (2) etching with a reversal mask of the underneath wiring pattern, and (3) chemical mechanical polishing. The two- to six-level wiring structures we fabricated, consisting of 300-nm-thick Nb and SiO 2 layers, had excellent layer flatness, independent of the wiring characteristics (width, length, and density). The electrical characteristics also remained at satisfactory levels, i.e., the leakage current between the Nb layers was sufficiently low. Two hundred to four thousand chains of stepwise and stacked contacts yielded a sufficiently large critical current, typically more than 10 mA at 4.2 K, which is two orders of magnitude larger than the critical current of Josephson junctions.

We fabricated Nb/AlO x /Nb junctions using electron cyclotron resonance (ECR) plasma etching. When junctions were fabricated using ECR plasma etching for the junction definition process, they exhibited leaky current–voltage ( I – V ) characteristics and poor critical current ( I c ) uniformity. This indicated that ECR plasma etching damaged the junction barrier. Excellent junction characteristics, on the other hand, were obtained by anodizing the junction periphery at 15 V after ECR plasma etching. This meant that the damaged region was within 14 nm from the junction periphery and that the leakage paths in the damaged region induced by ECR plasma were completely passivated by anodization. The uniformity of I c in junctions fabricated using ECR plasma etching and anodization was quite good. The standard deviation, 1 σ , in I c was estimated to be 1.4% for a series array of 1000, 0.93-μm 2 junctions with a critical current density of 9.8 kA/cm 2 .

Mechanical polishing (MP) is a key technology for fabricating multi-layer, large-scale integrated Nb SFQ circuits. This process, however, could possibly influence junction characteristics. We studied the impact of a planarization process based on MP on the junction characteristics. The process, performed either before or after junction fabrication, did not significantly degrade the junction characteristics. We successfully demonstrated multi-layer integrated circuits with six Nb layers planarized by MP.

We have been developing a 10-kA/cm2 advanced Nb process in order to fabricate larger scale and higher speed SFQ circuits with over 100k junctions. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, 4 Nb wiring layers, a Nb layer for DC power, a Nb ground plane, SiO2 insulator layers, and a Mo resistor layer. Process technologies for fabricating 1.0-μm2 junctions with high JC of 10 kA/cm2 and 1σ of 1.4% and Mo resistors with R□ of 2.4 Ω have been developed. A new planarization technology called caldera, which is applicable to patterns of various sizes, has been developed. This process consists of reactive ion etching (RIE) with a reverse mask, bias sputtering, and mechanical polishing planarization (MPP). We have now successfully developed all the component technologies required for the advanced Nb process. We have implemented these technologies for the through process and fabricated a structure with six planarized Nb layers, including Nb/AlOx/Nb junctions, Mo resistors, and contacts. In this structure, we obtained excellent current–voltage characteristics for the junctions, sufficient superconducting characteristics for the contacts, and good insulation characteristics between the wiring layers.

We have been developing a 10 kA cm−2 Nb advanced fabrication process to make larger scale and higher speed SFQ circuits that have over 100k junctions. The main challenges in implementing this process are related to increasing the critical current density of junctions, decreasing design rules and increasing the number of Nb layers. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, Nb wiring layers, Nb shield layers, a Nb layer for dc power, a Nb ground plane, SiO2 insulator layers and a Mo resistor layer. In fabricating this multi-layer structure, we have developed a new planarization technology which enables the flattening of the SiO2 insulator surface over the Nb wiring layer independent of the pattern sizes of the Nb wirings. This planarization technology consists of SiO2 bias sputtering, reactive ion etching with a reversal mask of the Nb wiring and mechanical polishing planarization. The SEM photographs showed excellent flatness for the planarized multi-layer structure.

We investigated an oversampling Σ – Δ A/D converter (ADC) with a large signal-to-noise ratio (∼80 dB or more) and a wide bandwidth (∼100 MHz), which were formed from single flux quantum circuits. The ADC consisted of a second-order lowpass Σ – Δ modulator and a third-order sinc decimation filter. A ladder circuit was utilized to supply the high frequency sampling clock signal of more than 16 GHz to the modulator. The third-order sinc filter was designed from a multistage decimation sinc filter and a multiple integration sinc filter. By combining both sinc filters, the sinc filter operating with a decimation factor of 16 at the high clock frequency of more than 16 GHz could be designed in the chip area of ∼10 × 10 mm 2 . Experimentally, we measured the bit rate of the ladder circuit from an average voltage measurement and an oscilloscope observation, and obtained the bit rate of 31 Gbps.

In order to establish double-loop feedback design, we have fabricated a prototype superconducting double-loop lowpass sigma-delta modulator. For digital feedback gain, multiple flux quanta are produced by a ladder circuit and carried through Josephson Transmission Lines (JTLs) to the feedback driver. The feedback driver consists of a single Josephson junction or two serially-connected junctions. Direct injection of the pulse current from the JTLs through a low-value resistor drives the feedback driver. The sigma-delta modulator was operated at the sampling frequency of 1.1 GHz and the measured power spectrum showed the noise shaping roughly of 12 dB/octave, which is characteristic of the second-order sigma-delta modulator.

We have been developing a superconducting band-pass sigma–delta modulator, which is the elementary circuit of the superconducting A/D converter. We have already obtained the noise-shaping characteristic of a superconducting band-pass modulator experimentally. In this paper we investigate the noise-shaping characteristic of the band-pass sigma–delta modulator from a circuit simulation, and compare it with the experimental results. We confirmed by the simulation that the designed band-pass modulator operated properly. The signal-to-noise ratio (SNR) of the superconducting band-pass modulator was improved by increasing the oversampling ratio. The SNR of 55 dB was obtained at the sampling frequency of 20 GHz and the bandwidth of 100 MHz from the simulation. It was found that the resonant frequency of the modulator decreased with the increase of the sampling frequency. For the design of the superconducting band-pass modulator, it is necessary to take account of this resonant frequency deviation.

We have improved an Nb 9-layer advanced process (ADP2) using a plasma-enhanced chemical vapor deposition (PECVD) SiO2 insulator. We could solve the problems due to the surface profile of the PECVD SiO2 by adding an ion-milling process. The reliability of the ADP2 was evaluated by the operating yield of the SFQ shift registers (SRs). The SRs with six different bit sizes from 16 to 2560 were designed to evaluate the circuit size dependency of their yields. The total number of SRs is 16, and the total number of junctions per chip is 68,990. By introducing the PECVD SiO2 insulator, we could obtain a high operating yield of more than 80% even for large-scale 2560-bit shift registers with more than 10,000 junctions. Moreover, we could obtain nine perfect chips (in which all the SRs in the chip functioned) out of 26 measured chips fabricated using the PECVD SiO2. From these results, we believe that the fabrication yield of the ADP2 is at a level of 100,000 Josephson junction circuits.