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β-Ga2O3, a promising ultra-wide bandgap material for future high-power electronics and deep-ultraviolet optoelectronics applications, has drawn tremendous attention in recent years due to its wide bandgap of ~ 4.8 eV, high breakdown electric field, and availability of substrates. However, the reported etch behavior of β-Ga2O3 and the quality of etched surfaces, as well as the associated interface characteristics, could limit the performance of β-Ga2O3 devices. In this article, the etchings of β-Ga2O3, including regular wet etching, photoelectrochemical etching (PEC), reactive ion etching (RIE) and metal-assisted chemical etching (MacEtch), are reviewed. A comparison of the etch rate, orientation dependence, aspect ratio, etching mechanism, and surface quality for each of these etching methods is presented and the step-by-step reactions in PEC and MacEtch are proposed to elucidate the etch mechanism. The challenges for these etching techniques for β-Ga2O3 are discussed.

Well isolated 72 nm pitch hexagonal honeycomb magnetic tunneling junction (MTJ) array with about 45 nm MgO CD was successfully fabricated on a DRAM platform by using mature DRAM array patterning solution with self-aligned double patterning technology and proposed triple hard mask scheme. The 72 nm pitch MTJ array had an equivalent cell size as small as $0.0044~\mu \text{m}$ 2, the world’s smallest pitch size and cell size for industrial MTJ array to our knowledge. The hexagonal array geometry offered considerably merit for storage density enhancement and MTJ etch convenience. A reactive ion etch (RIE) and ion beam etch (IBE) combined MTJ etching solution was adopted to optimize pillar isolation and mitigate metallic re-deposition and etch damage. Perpendicular magnetic anisotropy was maintained in MTJ array; however, free layer coercivity was smaller than expected, indicating the existence of etch damage or fringe magnetic field interaction. Potential challenges for the chip integration of high-density hexagonal MTJ array are also discussed.

The selectivity of the reactive ion etching of functional materials included in the device structures of nanoelectronics with respect to the mask of a negative e-beam resist based on hydrogen-silsesquioxane (HSQ) is studied. The formation of nanostructures with sub-50-nm critical dimensions under the HSQ mask is studied for a number of materials: monocrystalline silicon, metallic Ta layers, dielectric SiO2 layers, Al2O3, HfO2, Si3N4, and low-k porous dielectric based on organosilicate glass (OSG) on silicon substrates. It is established that HSQ resist masks can be used to manufacture prototypes of micro- and nanoelectronic devices with topological dimensions up to 10 nanometers using a wide range of materials, including creating structures with relatively high aspect ratios with an absolute thickness of the layers of functional materials of tens of nanometers.

The enhanced surface area of silicon nanotexture is an important metric for solar cell integration as it affects multiple properties including optical reflectance, dopant diffusion, and surface recombination. Silicon nanotexture is typically characterized by its surface-area-to-projected-area ratio or enhanced area factor (EAF). However, traditional approaches for measuring EAF provide limited statistics, making correlation studies difficult. In this article, silicon's dominant ultraviolet reflectance peak, R(E2), which is very sensitive to surface etching, is applied to EAF spatial mapping. A clear decay correlation between R(E2) and EAF is shown for multiple textures created using reactive ion etching and metal catalyzed chemical etching. This correlation is applied to R(280 nm) reflectance mapping to yield accurate, high-resolution full-wafer EAF spatial mapping of silicon nanotextures. R(280 nm) mapping is also shown to be sensitive enough to correlate the impact of nanotexture spatial variation on post-diffusion sheet resistance. Finite-difference time-domain simulations of several nanoscale pyramid textures confirm a decay band for R(E2) versus EAF, consistent with our measurements. We suggest that R(E2) mapping may prove useful for other silicon nanotexture properties and applications where EAF is important.

A comprehensive study of drain current dispersion effects in $\beta $ -Ga2O3 field-effect transistors (FETs) has been done using dc and pulsed measurements. Both the virtual gate effect in the gate–drain access region and mobile traps under the gate are the most plausible explanations for the experimentally observed pulsed current dispersion and high-temperature threshold voltage shift, respectively. Unpassivated devices show significant current dispersion between dc and pulsed ${I}$ – ${V}$ response in gate lag measurements characterized by time constants in the range of 400–690 $\mu \text{s}$ both at room temperature and higher temperatures. The increasing time constant with temperature suggests a complex electron capture and emission process in the virtual gate. The reactive ion etching step during the device fabrication is most likely responsible for introducing the traps. The effect of traps can be minimized by using surface passivation layers, in this case, silicon nitride, which shows significant improvement in the current dispersion. This work demonstrates the detrimental effect that the traps can have on the current dispersion, which significantly limits the high-frequency operation of the device.

Blazed gratings are widely used in optical detection devices with the unique property of concentration of light energy to a desired diffraction order. However, traditional substrates for fabricating blazed gratings are easily damaged with the wear and tear in long-term usage under harsh conditions. Here, we propose the fabrication of blazed gratings on sapphire with high mechanical stability by femtosecond laser lithography combined with subsequent reactive ion etching (RIE). Various sapphire blazed gratings with periods from 2 μm to 10 μm and heights from 260 nm to 2 μm were realized to concentrate light energy (wavelengths of 405 nm, 532 nm and 633 nm) to different diffraction orders (1st, 2nd, and 3rd). The results provide great insights for the construction of micro-optical devices that have potential applications under harsh conditions.

Fabrication of the disordered Si nanostructure arrays with a controlled randomness has gained research interest because the well-controlled disorder can provide more effective light trapping. The parabolic Si nanostructures were made by combining processes of silica self-assembled monolayer deposition and reactive ion etching. We demonstrate that the order of the Si nanostructure arrays can be varied in the nanosphere lithography by blending two different silica nanoparticles of 960 nm and 520 nm in diameter. The order of the Si nanostructure arrays was adjusted by varying the fractions of the small size nanoparticles. The light trapping performances were analyzed by measuring the total reflectances from the textured wafers and also simulated using optical simulations. Furthermore, we incorporated our disordered Si nanostructure arrays on ultrathin Si wafers of a 50-um thickness, and the influence of the disorder on the optical performances was discussed.

In this work, structure designs and the corresponding energy loss analysis are conducted to achieve the high-efficiency n-type rear-junction solar cells with polysilicon passivated contact. We focus on the front-side structure design of solar cells, considering that the primary efficiency loss of the conventional n-type polysilicon passivated contact cells with boron-diffusion emitter is from the front side. A well-designed rear-junction solar cell with front localized n-type and rear full-area p-type polysilicon passivated contacts is expected to overcome these problems. However, the efficiency of rear-junction solar cells is sensitive to the front-side electrode contact resistivity. To accurately assess the practically achievable efficiency that the current technology can reach, we develop a simple modified TLM with wet-chemical etching to measure the contact resistivity of the n-type polysilicon contact. This method does not require relatively expensive photolithography and reactive ion etching tools and is easy to be used. When the contact resistivity of the front-side localized n-type polysilicon contact reaches 0.002 Ω·cm2 with a saturation current density of ~10 fA/cm2 in the front-side un-diffused area, the efficiency of the rear-junction n-type solar cell is expected to be ~26%, showing its potential for application in mass-production of high-efficiency crystalline silicon solar cells.

Phase change random access memory (PCRAM) is one of the most industrially applicable memory devices because of its advantages such as non-volatility, high speed, scalability, and low power consumption. Ovonic threshold switch (OTS) materials are used in selector devices in PCRAM circuits and are generally composed of chalcogenide compounds. In this study, etch characteristics of OTS material composed of Ge-As-Te has been investigated using reactive ion etching (RIE) by hydrogen-based gases such as H2, CH4, NH3, etc. Among the investigated hydrogen-based plasmas, NH3 showed the highest etch rate due to the high vapor pressures of the hydrides of the OTS material, but the formation of nitride compound and the increased roughness were observed on the OTS surface. In the case of CH4 plasma, due to the carbon on the OTS surface, a polymer layer was deposited. Even though H2 showed the better surface smoothness due to the no surface residues or compounds on OTS surface related to carbon or nitrogen, the etch rates were lower than NH3. In this presentation, the effects of various hydrogen-based gases on the etch characteristics of OTS material will be discussed in details.

Light- and elevated temperature-induced degradation (LeTID) of silicon wafers reduces the energy yield of photovoltaic modules in the field. A previous study demonstrated that this degradation is greatly reduced in samples with a surface textured with black silicon formed via reactive ion etching. However, the reason for this reduction is currently not understood. This article extends that result to a range of nano-textures formed using commercial metal-catalyzed chemical etching. Lifetime test structures are fabricated on multicrystalline wafers with six different chemical nano-textures and the results are compared to planar reference samples. The article demonstrates a reduction in the extent of light-induced degradation compared to planar reference samples for all six textures. The extent of LeTID is observed to reduce with decreasing front surface reflectance and increasing front surface area. The article finds that wafer thickness, phosphorus gettering, and fast-firing cannot explain the result.

In this study, the deposition parameters of the SU8 2000.5 negative photoresists have been investigated and optimized for the photolithographic technique. Then, applied the inductive coupled plasma reactive ion etching (ICP RIE) to produce V-shaped groove diffraction grating on a silicon substrate. Spin coater (speed: 1000 rpm) was used to coat the photoresist over the Si substrate. The observed photoresist film thickness was measured by ellipsometry and found to be 800 nm. Interestingly, the film exhibited some stability with increasing the spin speed. The thermogravimetric analysis was used to optimize the baking temperature which was found to be ~105 °C. Contrast curves were obtained experimentally and used to optimize the exposure energy along with the images obtained from the field emission scanning electron microscopy (FESEM). The optimized energy fluence was found to be 17 mJ/cm2. It was interesting to observe that the thickness of the photoresists film was increasing with the elevation of the exposure energy fluence. The FESEM images were used to optimize the ICP RIE etching process and the best etching conditions for the Si substrate were ICP power: 150 W, bias power: 100 W, and SF6 gas flow rate: 32 SCCM (standard cubic centimeters per minute), O2 gas flow: 8 SCCM, and Ar gas flow of 8 SCCM. It is worth to mention that well-defined V-shaped grooves were observed with a depth of 2 μm under the same experimental conditions.

The zinc blend nonlinear crystal of zinc telluride (ZnTe) is currently one of the most commonly used electro-optical material for terahertz (THz) probe and imaging. We report herein how to engineer the surface behavior of a ZnTe single crystal to design subwavelength structures (SWSs) for enhancing ultrabroadband transmission. Polystyrene (PS) nanoparticle monolayers with a maximum coverage of 85.2% were produced on the ZnTe crystal by an eccentric spin-coating technique combined with surface wettability engineering. Subsequently, the well-defined conical SWS arrays were fabricated on the ZnTe crystal by reactive ion etching over the PS monolayer template, with the size of the SWS arrays customized by optimizing the etching process. Finally, we demonstrated ultrabroadband antireflection on the surface structured ZnTe crystals in the visible-near-infrared, infrared, and terahertz regions with transmittance increase of 11.6%, 10.0%, and 24.8%, which are attributed to the decrease of surface Fresnel reflection by SWS. Notably, in 0.2-1.0 THz, the transmittance reached over 70%. Our work provides a new strategy to enhance the THz generation efficiency and detection sensitivity based on ZnTe crystals by surface engineering.

Chip-scale SARS-CoV-2 testing was demonstrated using silicon nitride (Si3N4) nanoslot fluidic waveguides to detect a tagged oligonucleotide with a coronavirus DNA sequence. The slot waveguides were fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication processes, including multiscale lithography and selective reactive ion etching (RIE), forming femtoliter fluidic channels. Finite difference method (FDM) simulation was used to calculate the optical field distribution of the waveguide mode when the waveguide sensor was excited by transverse electric (TE) and transverse magnetic (TM) polarized light. For the TE polarization, a strong optical field was created in the slot region and its field intensity was 14× stronger than the evanescent sensing field from the TM polarization. The nanoscale confinement of the optical sensing field significantly enhanced the light-analyte interaction and improved the optical sensitivity. The sensitivity enhancement was experimentally demonstrated by measuring the polarization-dependent fluorescence emission from the tagged oligonucleotide. The photonic chips consisting of femtoliter Si3N4 waveguides provide a low-cost and high throughput platform for real-time virus identification, which is critical for point-of-care (PoC) diagnostic applications.

High-quality gallium nitride etching is highly desirable in electronic device fabrications. For the GaN base devices, the electronic properties largely depended on the etching induced surface damages. To overcome this, a controllable GaN etching method was developed using inductively coupled plasma reactive ion etching (ICP-RIE) by controlling radio frequency (RF) power, and DC bias. The etching rate, DC bias, and root-mean-square surface roughness were measured as a function of bias power under different RF, 40 and 13.56 MHz. The effects of ICP power and chlorine to argon percentage were systematically studied. An extremely slow etching rate and low-damage surface were achieved by reducing DC bias power to 25 W under RF 40 MHz. Ni|Au Schottky diodes were fabricated and characterized. The diode fabricated on the 40-MHz RF etching GaN surface has a much lower ideality factor and higher barrier height than non-etched GaN and RF 13.56 MHz etching GaN.

The micro/nano surface structure of triboelectric layers possesses a critical impact on the performance of triboelectric nanogenerators (TENG). Here, we present a solution for the enhancement of the triboelectric performance by utilizing a Q-switched Pulsed Laser (QSL) that directly writes on an Aluminum surface in the net configuration. The crinkled nanostructure of the surface of Polytetrafluoroethylene (PTFE) is fabricated by the Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) technology. By adjusting the QSL source parameters, many kinds of Al/PTFE concepts of synthetic devices with built-in contact-separation could systematically be characterized. The optimal triboelectric performance was confirmed by the increase of the open-circuit voltage and the short-circuit current from 75 V to 148 V and from 6.8 μA to 9.6 μA, respectively, and by a nearly 2.5 times higher power than that of a pristine Al-based device. The real-time practical applicability of the SA-TENG concept was confirmed by the lighting up of 92 LEDs connected in series and by the charging up of a 10 μF capacitor to 1.68 V in 30 s. This work provides an effective direct writing process with a Q-switched Pulsed Laser for the fabrication of micro/nano-structures on Aluminum and for the enhancement of the output performance of TENG, which would greatly promote the TENG branding in mass manufacturing and micro-energy utilizations.

Highly ordered silicon nanostructures were fabricated using the nanosphere mask and reactive ion etching method. A self-assembled SiO2 nanospheres monolayer obtained by spin-coating method was used...

Trapped light in an organic light-emitting diode (OLED) can be extracted through the construction of periodic structures on the substrates. However, these periodic structures can merely enhance the light emission of a specific wavelength, but not the white light for lighting application. In this work, indium tin oxide (ITO) with a corrugated structure is prepared by reactive ion etching of a polystyrene (PS) sphere matrix with diameters of 300 and 350 nm, which can apparently reduce the losses produced by the waveguide mode and surface plasmon polariton (SPP) mode in the RGB-based white OLED. The extractions of the waveguide mode and SPP mode are investigated theoretically and experimentally. This special corrugated ITO structure with the pitches of 300 and 350 nm, as an internal light out-coupling structure, is useful for the extraction of bluish green and red emission, respectively. More importantly, there are significant enhancements in both the current and power efficiencies of white OLEDs, and the CIE coordinates are located in the warm white region with different viewing angles. Using different weight ratios of the mixed PS spheres, the electroluminescent spectra of white OLEDs can be easily adjusted.

Etched-and-regrown GaN pn-diodes capable of high breakdown voltage (1610 V), low reverse current leakage (1 nA = 6 $\mu \text{A}$ /cm2 at 1250 V), excellent forward characteristics (ideality factor ~1.6), and low specific on-resistance (1.1 $\text{m}\Omega $ .cm2) were realized by mitigating plasma etch-related defects at the regrown interface. Epitaxial ${n}$ -GaN layers grown by metal-organic chemical vapor deposition on free-standing GaN substrates were etched using inductively coupled plasma etching (ICP), and we demonstrate that a slow reactive ion etch (RIE) prior to ${p}$ -GaN regrowth dramatically increases diode electrical performance compared to wet chemical surface treatments. Etched-and-regrown diodes without a junction termination extension (JTE) were characterized to compare diode performance using the post-ICP RIE method with prior studies of other post-ICP treatments. Then, etched-and-regrown diodes using the post-ICP RIE etch steps prior to regrowth were fabricated with a multi-step JTE to demonstrate kV-class operation.

The optical performance of fused silica optics used in high-power lasers is known to depend not only on their surface damage resistance, but also on their surface quality. Previous studies have shown that good fused silica damage performance and surface quality can be achieved by the use of reactive ion etching (RIE), followed by HF-based wet shallow etching (3 μm). In this study, two kinds of HF-based etchants (aqueous HF and HF/NH4F solutions) were employed to investigate the effect of HF-based etching on the optical performance of reactive-ion-etched fused silica surfaces at various HF-based shallow etching depths. The results showed that the addition of NH4F to HF solution makes it possible to produce a high-quality optical surface with a high laser-induced damage threshold, which is strongly associated with the surface roughness and fluorescence defect density. Additionally, changing the HF-based etching depth over the range from 1 μm to 3 μm can affect the surface damage resistance and absorption performance of RIE-treated fused silica. The light-scattering results indicate that the point defect density plays an important role in the determination of the HF-based etching depth. Understanding these trends can enable the advantages of the combined technique of RIE and HF-based etching during the fabrication of high-quality fused silica optics.

We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor—1X nm Quad-MTJ can achieve 10 years retention—while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 1011) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node.

We present the nanofabrication and transport properties of single silicon nanowires (NWs) having mean widths in the range from sub-30 to 500 nm. Hall effect measurements are undertaken in the magnetic fields of 14 T at 300 K. The NWs are defined by electron-beam lithography (EBL) using the negative tone resist hydrogen silsesquioxane (HSQ) as a mask for reactive ion etching (RIE). Silicon NWs are patterned on nonuniform highly doped n-type silicon-on-insulator (SOI) substrates. The doping profile has been observed to show a significant effect on the NW electrostatics, which in turn influences the contact and transport properties of the NWs. For the formation of Hall electrodes, we have employed an angled substrate evaporation technique, where the NW itself is used as a shadow mask and an intimate sidewall contact has been formed. The Hall electrodes are not opposite to each other in this case; therefore, the longitudinal resistance pickup had to be considered when extracting the Hall signal of the NW. The mobility of these NWs is discussed. For the narrowest 40-nm-wide silicon NW, the obtained value of mobility is 292 ± 6 cm2/Vs and, for the blanket, nonpatterned device layer, it is 100 ± 0.1 cm2/Vs. The effective mobility increases as the width of the NWs decreases. This is attributed to the reduced dimensionality of the electron transport in the NWs. Both the electrical and effective thicknesses of the NW change at small physical width, which results in enhanced electron transport within the channel and enhances the value of the measured Hall signal.

We introduce a deep-recessed gate architecture in $\beta $ -Ga2O3 delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) $\beta $ -Ga2O3 layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl3 plasma-based etching at ~5 W reactive ion etching (RIE) power to ensure minimal plasma damage. Etch damage incurred with plasma etching was mitigated by annealing in vacuum at temperatures above 600 °C. A gate-connected field-plate edge termination was implemented for efficient field management. Negligible surface dispersion with lower knee walkout at high ${V}_{{\text {DS}}}$ , and better breakdown characteristics compared to their unpassivated counterparts were achieved. A three-terminal OFF-state breakdown voltage of 315 V, corresponding to an average breakdown field of 2.3 MV/cm was measured. The device breakdown was limited by the field-plate/passivation edge and presents scope for further improvement. This demonstration of epitaxially passivated FET is a significant step for $\beta $ -Ga2O3 technology since the structure simultaneously provides control of surface-related dispersion and excellent field management.

Silicon nanoporous membranes provide the fundamental underlying technology for the development of an implantable bio-artificial kidney. These membranes, which are comprised of micromachined slit-pores that are nominally 10 nm wide, allow for high-efficiency blood filtration as well as immunoprotection for encapsulated cells. Our approach takes advantage of well-established semiconductor fabrication technology to give us precise dimensional control over pore widths, thereby enabling a highly selective filtration function and a clear path towards further miniaturization. This work builds on our prior results on “ribbed nanoporous membranes” by adding a second-level hierarchy of significantly taller “mega-ribs” to further strengthen the membranes. Relying on a two-step Deep Reactive Ion Etch (DRIE) process, we etch $4~\mu \text{m}$ -deep as well as $40~\mu \text{m}$ -deep trenches into a silicon substrate, grow a thermal oxide liner, and deposit a layer of polysilicon into this “mold” to form membranes which, when released after a backside DRIE etch, feature a network of reinforcing ribs on the underside. We have fabricated and tested freestanding membrane spans that are up to 14 times wider than before, with approximately double the measured permeability per unit area. The new architecture can also improve cross-membrane mass-transfer rates and reduce chip-fabrication costs. [2020-0170]

The article deals with the synthesis of silicon nanowires by the method of metal-assisted chemical etching (MACE). The purpose of this work is to use in light sensors silicon nanowires that synthesized by the MACE. To achieve this goal, it was necessary to synthesize silicon nanowires by the MACE and to study their structural features, to obtain diode structures based on silicon nanowires and to study their sensitivity to visible radiation, to establish the influence of technological parameters of the MSHT process on the sensitivity of photo sensors and sensors. Today, nanostructures are obtained by the method of reactive ion etching, electrochemical etching and plasma implantation. However, most of these methods require sophisticated process equipment. Metal-assisted chemical etching (MACE) method is very promising for nanostructures creation. Two-stage MACE was used to make the samples. In the first stage, silver nanoparticles were deposited on the surface of single crystalline silicon. In the second stage, the samples were etched in a solution of water, hydrogen peroxide and hydrofluoric acid and, as a consequence, a structured surface was obtained. It should be noted that the samples were treated at different times of each of the stages of MACE. Based on the obtained samples, diode light sensors with different photoelectric parameters were synthesized. For the sensors obtained, the sensitivity was calculated in the photodiode and photogenerator modes, and the volt-ampere, luxury-ampere characteristics and dependences of the current density on the illumination density were constructed. structured silicon has a mesh-like appearance, where the dark regions are gaps (pores) and the light ones are silicon (pore walls, nanowires). First, compare the samples with different deposition times. It is seen that as the deposition time of the particles increases from 10 to 40 s, a more developed silicon surface is formed. Also, with the duration of deposition 40s on the silicon surface there are needle-like formations, which according to the results in the work are silver dendrites. All the above characteristics were analyzed for the effect of the deposition time of silver particles t1 and etching time t2 on them. Studies have shown that the optimum technological conditions of metal assisted chemical etching of silicon for using in light sensors are the following conditions: the deposition time of silver particles 40c, etching time 30 min, the content of hydrogen peroxide in the second solution of 0.8 ml. This mode of synthesis of the structuring of silicon substrates provides maximum photosensitivity ratios both in the photodiode (1.53 mA / lmV) and in the photogenerator (304 mA / W) modes. The influence of the concentration of H2O2 used in the second stage is crucial only for the photocurrent, which is not critical, and the influence of the AgNO3 concentration in the first stage of MACE does not have a significant effect on the parameters.

Magnetic tunnel junctions (MTJs) patterned with 70 × 70 nm2 square arrays were etched in a CH4/O2/Ar gas mixture by pulse-modulated inductively coupled plasma reactive ion etching (ICPRIE). A good etch profile of MTJs with etch slope of approximately 82° was achieved by adjusting the on–off duty ratio of the plasma and pulse frequency. Langmuir probe analysis and optical emission spectroscopy confirmed that the balance between the formation of the passivation layer as an etch byproduct and sputtering effect is responsible for the etch selectivity and etch profile with a high degree of anisotropy. It is concluded that the application of pulse-modulated plasma on ICPRIE can be an effective method to obtain the anisotropic etch profile of nanometer-scale MTJs.

This article reports a novel work on the fabrication of microarrays of electrospun Poly(vinylidene fluoride) (PVDF) membrane for MEMS and energy harvesting applications. Micropatterning of PVDF membrane is an essential step in fabrication process in order for the sample to be integrated in microelectromechanical systems. The high $\beta $ -phase fraction of PVDF membranes was successfully synthesized by one step electrospinning technique. A new fabrication process for micropatterning of electrospun PVDF membrane is being proposed using dry reactive ion etching. Oxygen plasma was chosen as the feeding gas in investigation for high etching rate in PVDF microstructure fabrication process. Micropatterning dimensions of 200/500/ $200~\mu \text{m}$ with the height of over $50~\mu \text{m}$ and etching rate of $2~\mu \text{m}$ /min were achieved in this work. Details of the fabrication process are discussed. High etching rate of patterning process with the selected parameters can be achieved on the electrospun PVDF membranes. This work has demonstrated successful micropatterning and integration of PVDF membrane into MEMS, thus open the possibilities for various application such as for sensors and actuators utilizing polymer membrane. We have validated the capability of the micropatterned device as energy harvester in producing an open circuit voltage density of 1.42 $\text{V}\cdot \text{m}^{{-2}}$ at temperature of 310.15 K and wind speed of 1 $\text{m}\cdot \text{s}^{{-1}}$ . [2019-0180]

The kind of profile produced during the reactive ion etching of AlGaInN light-emitting-diode (LED) heterostructures on the surface that became free after removal of the growth substrate is studied in relation to the composition of the gas mixture used in the etching process. It is shown that using a mixture composed of Cl2 and Ar, taken in a 3:2 ratio in terms of flow rates, leads to the thinnest profile, whereas a 2 : 1 gas mixture of BCl3 and Ar provides the largest structural elements. To study the effect of the kind of profile on the quantum efficiency (QE), flip-chip LEDs are fabricated on a silicon substrate. The LEDs are etched in different modes after the growth substrate is removed. Etching in the Cl2:BCl3:Ar mixture with a flow ratio of 6:10:11, which leads to intermediate sizes of the etching profile elements, is optimal for obtaining maximum light extraction from a LED chip at a wavelength of 460 nm. The variation of the kind of profile with the gas-mixture composition suggests that the profile parameters can be tuned to the wavelength used. An analysis of how the QE of LED chips depends on the etching duration in the three-component mixture under consideration results in that the optimum etching duration is estimated to be ~30 min. The results of the study can also be of use in the search for conditions minimizing the reflection of incident light by a chip, e.g., for photodetectors.

We study and fabricate graphene nanowalls/silicon hybrid heterojunction photoconductive detector to provide process technology of the device and theoretical foundation for the purpose of preparation of high-performance photodetectors. The graphene nanowalls (GNWs) film is patterned by double-layered photoresist-based photolithography and reactive ion etching (RIE) process to achieve high quality GNWs channel and fabricate three different GNWs/Si heterojunction photoconductive detectors with n-doped, intrinsic and p-doped silicon substrates (n-Si, i-Si, p-Si), respectively. The GNWs film not only acts as a photoconductive channel for carrier transport, but also constructs a Schottky heterojunction with the silicon to participate in the separation and transport of photogenerated carriers. Since the injection of holes needs to pass through the Schottky junction region, the height of the Schottky barrier determines the injection ability of photogenerated carriers, which directly affects the photoconductive gain of the GNWs and silicon. In addition, under low bias VDS, the GNWs/n-Si photoresponse current is maximum and the GNWs/p-Si photoresponse current is minimum. The photoresponse is attributed to the barrier heights of the GNWs/n-Si, GNWs/i-Si, and GNWs/p-Si with values of 0.73 eV, 0.69 eV, and 0.63 eV, respectively. The higher the barrier, the more the number of photogenerated carriers injected into the GNWs will be, and the photoresponse current is large as well.

Since the outbreak of the severe respiratory disease caused by the novel coronavirus (COVID-19), the use of face masks has become ubiquitous worldwide to control the rapid spread of this pandemic. As a result, the world is currently facing a face mask shortage, and some countries have placed limits on the number of masks that can be bought by each person. Although the surgical grade N95 mask provides the highest level of protection currently available, its filtration efficiency for sub-300 nm particles is around 85% due to its wider pore size (∼300 nm). Because the COVID-19 virus shows a diameter of around 65–125 nm, there is a need for developing more efficient masks. To overcome these issues, we demonstrate the development of a flexible, nanoporous membrane to achieve a reusable N95 mask with a replaceable membrane and enhanced filtration efficiency. We first developed a flexible nanoporous Si-based template on a silicon-on-insulator wafer using KOH etching and then used the template as a hard mask during a reactive ion etching process to transfer the patterns onto a flexible and lightweight (

The experimental data on the plasma etching of Si3N4 for sub-100 nm gate fabrication for high electron mobility transistors (HEMTs) based on InAlN/GaN heterostructures are analyzed. The influence of the plasma etching process parameters on the plasma-induced damage to the InAlN/GaN heterostructure is considered. The possibility of formation of a 70 nm-length gate InAlN/GaN HEMT using low damage reactive ion etching of Si3N4 is demonstrated.

Reactive Ion Etching (RIE) of Cytop as the cladding material for optical waveguides and microfluidic channels is investigated. Different grades of Cytop (M, A and S), different mask materials including photoresist and metals, different RIE parameters, along with different substrate materials were investigated. Grass-like structure was observed at the bottom of etched channels, of height that depends on the etching process parameters. A comprehensive post-etch acid cleaning procedure was devised to effectively remove the grass structure. [2019-0232]

All-dielectric nano-structures have recently gained much attention in meta-material related research. Experimental observations of Mie-scattering resonances in high-refractive-index dielectric nanoparticles led to a rapid advancement of this research field. Due to its high-refractive-index and significant technological involvements, silicon in particular has emerged as a prevailing material. Here, we demonstrate an all-silicon subwavelength structural coloration technique harnessing the resonant interaction between white light and individual silicon nano-object. Furthermore, square matrices with a resolution of more than 50,000 dpi were achieved using a 500 × 500 nm 2 color pixel. The 500 nm period was to avoid significant coupling between adjacent silicon nano-objects, thus allowing us to investigate the scattering colors of individual all-silicon nano-resonators.

Silicon solar cell texturing is the process of reducing the light reflection of the solar cells by changing their surface structure. Given that multi-crystalline silicon (mc-Si) wafers have grains with different orientations, their texturing process is more difficult to realize compared with those of monocrystalline silicon (mono-Si) wafers. There are two types of texturing processes: wet and dry texturing. Acidic solution-based wet-textured mc-Si samples have higher reflectance values than mono-Si wafers. However, the reactive ion etching (RIE)-texturing of mc-Si wafers has the advantage of decreasing reflectance to values below 10%. Despite this decrease in reflectance, RIE byproducts and plasma-induced damage bring about recombination that results in a decrease the passivation properties of the solar cell. In this study, the RIE byproducts as well as the plasma-induced damage of the RIE-textured mc-Si wafers were analyzed using SEM, STEM, and EDS analysis, while quasi-steady-state photoconductance (QSSPC) was used to confirm the optical characteristics of the RIE-textured mc-Si wafers. Additionally, HF treatment resulted in byproduct removal, and a relatively high implied Voc (673 mV) was confirmed within 3 min of HF treatment. The defect removal etching (DRE) process using KOH was applied to remove the lattice defect layer, and after 40 s of the DRE treatment, the implied Voc increased to ~ 680 mV. Thus, the RIE-textured mc-Si solar cell showed a power conversion efficiency of 19.6%, which was ~ 0.6% higher than that of acid-textured mc-Si solar cells based on the increase in short-circuit current (Isc).

We have proposed a novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor $\Delta $ and switching efficiency defined as the ratio of $\Delta $ to intrinsic critical current ${I}_{\text {C0}}$ ( $\Delta /{I}_{\text {C0}}$ ) by a factor of 1.5–2 compared with the conventional double-interface MTJ technology. The free layer of the developed quad interface consists of bottom-MgO/FL1/middle-MgO/FL2/top-MgO stack structure. We successfully fabricated the quad-interface MTJ using a 300-mm process based on a novel low-damage integration process including physical vapor deposition (PVD), reactive ion etching (RIE), and so on. By developing the quad-interface MTJ, we have achieved about two times larger $\Delta $ and $\Delta /{I}_{\text {C0}}$ at the same time. Moreover, we have achieved about two times larger tunnel magnetoresistance (TMR) ratio at the same resistance area (RA) product by developing the FL1, bottom-MgO, and middle-MgO. The developed quad-interface MTJ technology considered as post-double-interface MTJ technology will become an essential technology for the scaling of the spin-transfer-torque magnetoresistive random access memory (STT-MRAM) beyond 20 nm.

We recently demonstrated an ultra-thin solar cell with increased radiation tolerance as compared to a traditionally thick absorber counterpart. However, as the active region of the device was reduced so was the absorption with respect to state of the art devices. Therefore, we discuss a light trapping design, which implements nanosphere natural photolithography to fabricate a micropillared diffraction grating, combined with a transparent spacer layer and a distributed Bragg reflector. We discuss the fabrication process and illustrate the effectiveness of integrating light trapping structures for enhanced optical confinement within an ultra-thin solar cell design.

Dry etching is a prevalent technique for pattern transfer and material removal in microelectronics, optics and photonics due to its high precision material removal with low surface and subsurface damage. These processes, including reactive ion etching (RIE) and plasma etching (PE), are performed at vacuum conditions and provide high selectivity and vertical side wall etched patterns but create high costs and efforts in maintenance due to the required machinery. In contrast to electrically generated plasmas, laser-induced micro plasmas are controllable sources of reactive species in gases at atmospheric pressure that can be used for dry etching of materials. In the present study, we have demonstrated the laser-induced plasma etching of monocrystalline silicon. A Ti:Sapphire laser has been used for igniting an optically pumped plasma in a CF4/O2 gas mixture near atmospheric pressure. The influence of process parameters, like substrate temperature, O2 concentration, plasma-surface distance, etching duration, pulse energy and crystal orientation on etching rate and surface morphology has been investigated. Typical etching rates of 2–12 µm x min−1 can be achieved by varying mentioned parameters with a decreasing etching rate during the process. Different morphologies can be observed due to the parameters set, smooth as well as rough surfaces or even inverted pyramids. The presented etching method provides an approach for precise machining of silicon surfaces with good surface qualities near atmospheric pressure and sufficiently high material removal rates for ultraprecise surface machining.

In this study, we fabricated embedded titanium dioxide ( T i O 2 ) nanograting structures with slanted cross section on a silicon dioxide ( S i O 2 ) substrate using electron beam lithography (EBL) and reactive ion etching (RIE) methods, and we analyzed their optical signals. The surface morphologies of the embedded T i O 2 nanograting structures were monitored by a scanning optical microscope (SEM). By focusing the transverse electric (TE) polarized beam with the wavelength λ = 633 n m at the incident angle θ = 22.0 ∘ from the rear side of T i O 2 face, we could observe + 1 st and − 2 nd diffraction orders with diffraction efficiencies ( I / I t o t a l ): I 1 = 23 % and I 2 = 19 % , respectively, on a S i O 2 / T i O 2 interface. Diffraction beams were waveguided to both left and right directions in a S i O 2 substrate via total internal reflection (TIR); next, two guided beams were emitted from the side edges of the substrate. This work is expected to develop a highly efficient two-way waveguide optical interconnector.

Due to its high theoretical specific capacity, a silicon anode is one of the candidates for realizing high energy density lithium-ion batteries (LIBs). However, problems related to bulk silicon (e.g., low intrinsic conductivity and massive volume expansion) limit the performance of silicon anodes. In this work, to improve the performance of silicon anodes, a vertically aligned n-type silicon nanowire array (n-SiNW) was fabricated using a well-controlled, top-down nano-machining technique by combining photolithography and inductively coupled plasma reactive ion etching (ICP-RIE) at a cryogenic temperature. The array of nanowires ~1 µm in diameter and with the aspect ratio of ~10 was successfully prepared from commercial n-type silicon wafer. The half-cell LIB with free-standing n-SiNW electrode exhibited an initial Coulombic efficiency of 91.1%, which was higher than the battery with a blank n-silicon wafer electrode (i.e., 67.5%). Upon 100 cycles of stability testing at 0.06 mA cm−2, the battery with the n-SiNW electrode retained 85.9% of its 0.50 mAh cm−2 capacity after the pre-lithiation step, whereas its counterpart, the blank n-silicon wafer electrode, only maintained 61.4% of 0.21 mAh cm−2 capacity. Furthermore, 76.7% capacity retention can be obtained at a current density of 0.2 mA cm−2, showing the potential of n-SiNW anodes for high current density applications. This work presents an alternative method for facile, high precision, and high throughput patterning on a wafer-scale to obtain a high aspect ratio n-SiNW, and its application in LIBs.

Silicon carbide (SiC) nanostructure is a type of promising field emitter due to high breakdown field strength, high thermal conductivity, low electron affinity, and high electron mobility. However, the fabrication of the SiC nanotips array is difficult due to its chemical inertness. Here we report a simple, industry-familiar reactive ion etching to fabricate well-aligned, vertically orientated SiC nanoarrays on 4H-SiC wafers. The as-synthesized nanoarrays had tapered base angles &gt, 60°, and were vertically oriented with a high packing density &gt, 107 mm−2 and high-aspect ratios of approximately 35. As a result of its high geometry uniformity—5% length variation and 10% diameter variation, the field emitter array showed typical turn-on fields of 4.3 V μm−1 and a high field-enhancement factor of ~1260. The 8 h current emission stability displayed a mean current fluctuation of 1.9 ± 1%, revealing excellent current emission stability. The as-synthesized emitters demonstrate competitive emission performance that highlights their potential in a variety of vacuum electronics applications. This study provides a new route to realizing scalable field electron emitter production.

Production of high-aspect-ratio silicon (Si) nanowire-based anode for lithium ion batteries is challenging particularly in terms of controlling wire property and geometry to improve the battery performance. This report demonstrates tunable optimization of inductively coupled plasma reactive ion etching (ICP-RIE) at cryogenic temperature to fabricate vertically-aligned silicon nanowire array anodes with high verticality, controllable morphology, and good homogeneity. Three different materials [i.e., photoresist, chromium (Cr), and silicon dioxide (SiO2)] were employed as masks during the subsequent photolithography and cryogenic ICP-RIE processes to investigate their effects on the resulting nanowire structures. Silicon nanowire arrays with a high aspect ratio of up to 22 can be achieved by tuning several etching parameters [i.e., temperature, oxygen/sulfur hexafluoride (O2/SF6) gas mixture ratio, chamber pressure, plasma density, and ion energy]. Higher compressive stress was revealed for longer Si wires by means of Raman spectroscopy. Moreover, an anisotropy of lattice stress was found at the top and sidewall of Si nanowire, indicating compressive and tensile stresses, respectively. From electrochemical characterization, half-cell battery integrating ICP-RIE-based silicon nanowire anode exhibits a capacity of 0.25 mAh cm−2 with 16.67% capacity fading until 20 cycles, which has to be improved for application in future energy storage devices.

The paper describes methods for manufacturing of diffractive optical elements by means of only "dry" processes starting from direct laser writing on titanium-containing films. According to first approach, direct laser writing onto thin Ti film forms surface oxide mask. Reactive ion etching removes non-oxidized Ti film and develops "latent" oxidized image. Subsequent thermal annealing of the oxidized Ti structure in air makes the mask more stable for following reactive ion etching of fused silica substrate to ensure proper phase depth of the binary diffractive structure. This makes it possible to avoid liquid etching, which reduces the yield and accuracy. The phase structure of the diffractive elements manufactured using the described method consists of the grooves etched in the fused silica substrate between ridges covered by TiO2 between them. We found out also that covering the Ti film by very thin Si layer helps to increase laser energy absorption at direct writing and creates quite resistant masking layer TiSi2 for the reactive ion etching. Preliminary estimates show that dual layer Si/Ti films can be used to create amplitude reflective DOEs. Possible application area for the developed methods is manufacturing of the diffractive optical elements used for precision generation of reference wavefronts in interferometric measurements of spherical and aspherical surfaces.

We present investigations of optical properties of black silicon (b-Si) nanostructures passivated with several high-k metal oxides (Al 2 O 3 , TiO 2 , HfO 2 and Sc 2 O 3 ), obtained by atomic layer deposition (ALD) method. The reflectivity was studied using the finite difference time domain (FDTD) method as well as experimentally, where Si wafers was structured by reactive ion etching method for b-Si fabrication. Modeling and measurements show improvements in the antireflection properties of thin-film/b-Si nanostructures over a wide range of light wavelengths. TiO 2 , HfO 2 and Sc 2 O 3 films provide a good alternative to Al 2 O 3 as passivating materials and antireflection coatings.

A lithography-free, self-assembly fabrication route exploiting black silicon (B-Si) microstructures to design a perfect absorber based on densely and disordered packed gold nanoparticles (AuNPs)-modified silicon forests have been proposed in this paper. The geometrical dimensions of microstructures were controlled by altering the flow rate of SF6/O2 in the reactive ion etching (RIE) chamber. The RIE B-Si shows a unique geometry that consists of a combination of sharp “needles” at the top and rounded “holes” at the bottom, and also shows an excellent adaptive relationship with Au deposition. By combining the light-trapping capability of the B-Si and the plasmonic nature of AuNPs in the near-infrared (NIR) range, an experimental absorption of 96.5% is achieved in a wide range from 350 to 2500 nm. This material has the potential for photonic applications, including solar energy harvesting or NIR-sensitive optoelectronic devices.

This paper reports the development of fiber optical hydrogen sensors using palladium and gold alloy nanostructures as sensor materials for hydrogen measurements using a D-shaped fiber as a platform. Using a maskless reactive ion etching technique, silica nanocone structures were formed on the surface of the D-shaped fiber. Palladium and gold alloys were deposited on the surface of nanostructured D-shaped fiber to form a nano-alloy sensor film. Evanescent interaction between guided light propagated in the fiber core and nano-alloy enabled highly sensitive hydrogen detection from concentrations that ranged from 0.25% to 10% in atmosphere pressure. The formation of nanostructured alloy enabled by the nanocone surface led to more than 3 times faster in sensor response time and significant improvements in sensor sensitivity and reversibility. The work presented here demonstrates that highly controllable VLSI microfabrication schemes can be applied to produce nanostructured sensor films on optical fibers for high-sensitivity chemical sensing.

A newly developed nanopatterned broadband antireflective (AR) coating was fabricated on the front side of a glass/indium tin oxide/perovskite solar cell (PSC) by depositing a single interference layer onto a two-dimensional (2D)-patterned moth-eye-like nanostructure. The optimized developed AR nanostructure was simulated in a finite-difference time domain analysis. To realize the simulated developed AR nanostructure, we controlled the SiO2 moth-eye structure with various diameters and heights and a MgF2 single layer with varying thicknesses by sequentially performing nanosphere lithography, reactive ion etching, and electron-beam evaporation. Optimization of the developed AR nanostructure, which has a 100 nm-thick MgF2 film coated onto the SiO2 moth-eye-like nanostructure (diameter 165 nm and height 400 nm), minimizes the reflection loss throughout the visible range. As a result, the short-circuit current density (JSC) of the newly AR-coated PSC increases by 11.80%, while the open-circuit voltage (VOC) remains nearly constant. Therefore, the power conversion efficiency of the newly developed AR-decorated PSC increases by 12.50%, from 18.21% for a control sample to 20.48% for the optimum AR-coated sample. These results indicate that the newly developed MgF2/SiO2 AR nanostructure can provide an advanced platform technology that reduces the Fresnel loss and therefore increases the possibility of the commercialization of glass-based PSCs.

In this paper, we study the technological process of separating a heteroplate from a polycrystalline diamond film (PDF-Si), separating a whole plate from sacrificial silicon. The hole formation in a diamond substrate from PDF via laser milling and plasma-chemical etching is studied. Plasma-chemical etching provided batch hole fabrication based on planar technology and precision lithography. The technological modes of hole etching through an aluminum mask via reactive ion etching with an inductively coupled plasma source (RIE-ICP) were optimized. The hole etching rate in the PDF was ~ 1.1 μm/min. A mathematical model of the technological process is developed. Etching is shown to occur mainly in oxygen. The technological process is adapted for the plasma-chemical etching setup “Plasma TM5”. The possibility of etching in a PDF holes 100 μm in diameter and more than 300 μm deep was studied. The etching rate was shown to depend on the hole depth and is nonlinear in nature, with etching of the hole walls and the aluminum mask.

Gold nanostructure arrays were fabricated by combining colloidal lithography with inclined reactive ion etching and inclinded sputtering. Field emission scanning electron microscopy studies of this substrate show uniaxial hexagonally ordered graded nanostructure arrays with increasing interstice at different positions. Optical spectroscopy studies in visible range reveal that these structures support localized surface plasmon resonance, surface plasmon polaritons, and hybridized modes. Optical spectra were found at each position along the direction of increasing interstice size, and the resonances tend to redshift with position. Different morphologies lead to 50 nm spectral tunability across 10 mm length of the substrate. Based on spectral resolution, optimum peak arising due to localized surface plasmon resonance in reflectance was selected for refractive index sensing application. The sensitivity and figure of merit were evaluated at each position. The sensitivity was found to increase accompanied by decrease in figure of merit with position. The highest sensitivity of 621.6 nm/RIU is obtained for the structure in which interstice size is maximum.

Perovskite solar cells (PSCs), which have surprisingly emerged in recent years, are now aiming at commercialization. Rapid, low-temperature, and continuous fabrication processes that can produce high-efficiency PSCs with a reduced fabrication cost and shortened energy payback time are important challenges on the way to commercialization. Herein, we report a reactive ion etching (RIE) method, which is an ultrafast room-temperature technique, to fabricate mesoporous TiO2 (mp-TiO2) as an electron transport layer for high-efficiency PSCs. Replacing the conventional high-temperature annealing process by RIE reduces the total processing time for fabricating 20 PSCs by 40%. Additionally, the RIE-processed mp-TiO2 exhibits enhanced electron extraction, whereupon the optimized RIE-mp-TiO2-based PSC exhibits a power conversion efficiency (PCE) of 19.60% without J-V hysteresis, when the devices were optimized with a TiCl4 surface treatment process. Finally, a flexible PSC employing RIE-mp-TiO2 is demonstrated with 17.29% PCE. Considering that the RIE process has been actively used in the semiconductor industry, including for the fabrication of silicon photovoltaic modules, the process developed in this work could be easily applied toward faster, simpler, and cheaper manufacturing of PSC modules.