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Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today’s countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, today’s countermeasures that count the frequency of activation of memory rows cannot identify the IP that launches the attack from the FPGA. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes 6.3% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA, when multiple IPs are monitored.

Near InfraRed (NIR) photon emission is observed from filaments in HfO2 Resistive Random Access Memories (ReRAMs). This technique is non-destructive and offers rapid localization of filaments, enabling statistical analysis of their spatial distribution. We show that the emission is electric-field driven. We also report direct experimental evidence of ${i}$ ) completely random spatial distribution of filaments across multiple devices and ii ) formation of multiple filaments inside a single large device.

In this paper, we discuss the use of spontaneous photon emission microscopy (PEM) for observing filaments formed in HfO2 resistive random access memory (ReRAM) cells. The setup employs a CCD and an InGaAs camera, revealing photon emissions in both forward (set) and reverse (reset) bias conditions. Photon emission intensity is modeled using an electric-field equation and inter-filament distance and density are determined assuming a uniform spatial distribution. The paper also discusses the use of high frame rate and prolonged photon emission measurements to assess lifetime and reliability and explains how single filament fluctuations and multiple filaments in a single cell were observed for the first time.

The globalization of IC manufacturing has increased the likelihood for IP providers to suffer financial and reputational loss from IP piracy. Logic locking prevents IP piracy by corrupting the functionality of an IP unless a correct secret key is inserted. However, existing logic-locking techniques can impose significant area overhead and performance impact (delay and power) on designs. In this work, we propose BISTLock, a logic-locking technique that utilizes built-in self-test (BIST) to isolate functional inputs when the circuit is locked. We also propose a set of security metrics and use the proposed metrics to quantify BISTLock’s security strength for an open-source AES core. Our experimental results demonstrate that BISTLock is easy to implement and introduces an average of 0.74% area and no power or delay overhead across the set of benchmarks used for evaluation.

Time-Resolved Emission (TRE) measurements for circuit debugging, fault localization, and circuit characterization are discussed along with recent detectors developments that have improved their low-voltage sensitivity, while maintaining an excellent jitter and low noise performance. Advantages and disadvantages of TRE methodologies are discussed and contrasted with laser probing techniques. 14 NM test cases are presented for logic debug, SRAM characterization, and early technology development. Finally, several advanced applications that are mostly unique to TRE are summarized. TRE has a unique capability to contribute to test and diagnostics applications, especially when conditions make laser-based technique difficult to use due to its invasiveness and the lack of resolution.

Heterogeneous SoCs integrate FPGAs and microprocessor cores on the same fabric to accelerate applications such as cryptography and deep learning. Since FPGAs share resources with the microprocessor cores, they can launch non-cacheable SDRAM transactions through direct FPGA-to-microprocessor SDRAM interface. Therefore, if the FPGA 3rd party IPs (3PIPs) are malicious, they can launch rowhammer attacks on the SDRAM. Today's countermeasures based on performance counters cannot detect these attacks because memory transactions from FPGAs do not pass through the cache. In addition, countermeasures that count the frequency of activation of memory rows require structural changes to the memory controller or DRAM chips. Moreover, today's countermeasures cannot identify the IP that launches the attack. We present a security solution that monitors the SDRAM transactions from IPs on the FPGA to each bank of the microprocessor SDRAM through the FPGA-to-microprocessor SDRAM interface. The proposed monitor is implemented on the FPGA fabric. It can detect attempts to launch a rowhammer attack before it causes bit flips in the SDRAM. It utilizes only 1% of the adaptive logic modules (ALMs) available in an Intel Cyclone V FPGA to monitor the transactions from one IP.

This study investigates the potential of AMSR-E surface soil moisture (SSM) time series data to distinctively identify paddy rice pixels and map paddy rice cultivated area at national scales. Taking China as the test site, we first established and applied a paddy rice planting index (PRPI) to each AMSR-E 25 km pixel over the entire country during the period 2003–2011. A mathematical model was then constructed for the retrieval of paddy rice cultivated area at the AMSR-E pixel scale using data obtained from PRPI as input, and a high coefficient of determination (R2 = 0.86) was recorded at the national scale. Provincial scale validation of the modeled paddy rice fraction shows a high correlation coefficient (R) of up to 0.94. In a subsequent step, the inter-annual variations in AMSR-E retrieved paddy rice areas were evaluated with annual agricultural census data, and an R-value of 0.93 was recorded. A good performance of the proposed retrieval method was also recorded when validated against MODIS paddy rice distribution images, and in which, five out of the seven selected validation sub-regions, had R-values larger than 0.85, while R-values of up to 0.70–0.75 were recorded in the other two. The results demonstrate that the proposed method is effective in mapping paddy rice agriculture at national scales, and therefore, the applicability of the PRPI algorithm on mapping paddy rice at continental and global scales is worth investigating.

Satellite-derived land surface temperature (LST) data are most commonly observed in the longwave infrared (LWIR) spectral region. However, such data suffer frequent gaps in coverage caused by cloud cover. Filling these ‘cloud gaps’ usually relies on statistical re-constructions using proximal clear sky LST pixels, whilst this is often a poor surrogate for shadowed LSTs insulated under cloud. Another solution is to rely on passive microwave (PM) LST data that are largely unimpeded by cloud cover impacts, the quality of which, however, is limited by the very coarse spatial resolution typical of PM signals. Here, we combine aspects of these two approaches to fill cloud gaps in the LWIR-derived LST record, using Kenya (East Africa) as our study area. The proposed “cloud gap-filling” approach increases the coverage of daily Aqua MODIS LST data over Kenya from &lt, 50% to &gt, 90%. Evaluations were made against the in situ and SEVIRI-derived LST data respectively, revealing root mean square errors (RMSEs) of 2.6 K and 3.6 K for the proposed method by mid-day, compared with RMSEs of 4.3 K and 6.7 K for the conventional proximal-pixel-based statistical re-construction method. We also find that such accuracy improvements become increasingly apparent when the total cloud cover residence time increases in the morning-to-noon time frame. At mid-night, cloud gap-filling performance is also better for the proposed method, though the RMSE improvement is far smaller (&lt, 0.3 K) than in the mid-day period. The results indicate that our proposed two-step cloud gap-filling method can improve upon performances achieved by conventional methods for cloud gap-filling and has the potential to be scaled up to provide data at continental or global scales as it does not rely on locality-specific knowledge or datasets.

In this paper, we present the first prototype of a Scanning Time-Resolved Emission (STRE) system consisting of a high-sensitivity, low-noise, and low-jitter single-point Superconducting Single-Photon Detector (SSPD) combined with a specialized scanning head of a Laser Scanning Microscope (LSM). This idea was first proposed in late 2006 [1] but required the right combination of detector, customization, and collaboration with a tool vendor to get to fruition. It should be understood that this is still a prototype system under development and significant improvements in acquisition time, resolutions, and performance are expected in the near future. In this paper, we will also present the first preliminary results acquired using a test chip fabricated in 32 nm SOI.

In this paper, we study the impact of humidity penetration into ICs (i.e., 14 nm SOI digital ring oscillators and 22 nm SOI mixed-signal LC-tank voltage-controlled oscillators) using controlled breaches of the chip barrier. Based on data collected from more than 460 samples, we found that the humidity penetration causes the performance of the circuit to be reduced (1-3%) because of the BEOL capacitance increase, while no detectable impact on the overall circuit lifetime is observed because of FEOL BTI and GOX mechanisms dominance.

This paper is a case study of diagnostic techniques used to debug a particularly difficult fail in a multi-port register file memory that appeared to increase its minimum functional voltage (VMIN) over time. Some of the debug techniques used involved Array Built-In-Self Test (ABIST) before and after chips in burn in, CPA (Critical Parameters Analysis), PEM (Photon Emission Microscopy), PICA (Picosecond Image Circuit Analysis) and PFA (Physical Failure Analysis).

The term CyberSecurity means many different things to many people - some think of data security, some think of identity protection, some think of intrusion attacks on the internet or USB ports. In reality, CyberSecurity represents any type of attack on computing machines. One of the type of attacks that is often overlooked are attacks by the supply chain to inject malfeasant circuitry into semiconductor devices as they are made. This is the one aspect of Design- for-Security and Design-for- Trust that is usually ignored. This innovative practice session will highlight three talks on hardware CyberSecurity attacks and defenses from both industry and academia.

In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.

A sub-threshold quiescent current (IDDQ) signature is observed for the first time. 14 nm SOI Ring Oscillators (ROs) are used to study a characteristic knee/peak for different device types and threshold voltages undergoing different stress conditions. The relationship of the sub-threshold IDDQ characteristics to process variability and aging are explained with detailed circuit level simulations. This novel signature has potential applications for reliability analysis and aged/used chip detection.

Spontaneous near infrared (NIR) emission is used for measuring transistor channel temperature in ICs. Emission modeling and data analysis are leveraged to estimate the peak temperature and thermal time constant inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip with high spatial and temporal resolution, without the need for circuit modifications or dedicated on-chip sensors. This method can be used to model heat dissipation during early process development, to localize hot spots, to calibrate on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.

This paper analyzes the root cause of performance degradation and the impact of hot-carrier injection (HCI) on the lifetime prediction of an $LC$ voltage-controlled oscillator ( $LC$ -VCO). Observed from both constant voltage stress and ramped voltage stress tests, it is shown that the dominant degradation mechanism shifts from a negative bias temperature instability to an HCI due to the accelerated aging condition. Furthermore, simulations show that a frequency increase of degraded VCO is mainly attributed to the degradation in the pMOSFET of a cross-couple pair, while the degradations in the pMOSFET and nMOSFET have relatively the same impact on the startup voltage shift. Compared with the frequency change, the degradation of the startup voltage of an $LC$ -VCO is less sensitive to device width. Based on the observed results, methodologies to optimize the reliability tests and mitigate the frequency shift of $LC$ -VCO are proposed.

Launching the evaluation research of green transportation can grasp the green transportation implementation accurately and diagnose the existing problems. From the perspective of green transportation, this research chose Dongguan “motorcycle ban” policy as the research object, and constructed secondary evaluation index system in transportation and environmental harmony, transportation and future harmony, transportation and society harmony, transportation and resource harmony, four dimensions. Then it used fuzzy comprehensive evaluation model to do the evaluation and found that the policy’s positive effect on the Dongguan green transportation development was average. Finally, based on the evaluation results, measures and advices were proposed.

In this paper, we present a technique for device temperature measurement using spontaneous near infrared (NIR) emission from an Integrated Circuit (IC). By leveraging modeling and data analysis, time-integrated emission measurements are used to estimate the temperature increase due to switching activity inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip without the need for circuit modifications or dedicated on-chip sensors and with a higher spatial resolution than thermal cameras. This method has important applications for modeling heat dissipation during early process development, localizing hot spots, calibrating on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.

In this work, we demonstrate the effectiveness of deconvolution algorithms in improving the spatial resolution of time-integrated emission images from integrated circuits. A mathematical model of the Point Spread Function (PSF) encompassing both the optical system and the imaging detector properties is used for the deconvolution process. Tuning of the PSF parameters is achieved through the minimization of dedicated cost functions that optimize image resolution while suppressing artifacts in the deconvoluted images. The optimized PSF is then used in both the Lucy-Richardson (L-R) and blind deconvolution algorithms. Results from 32 nm and 14 nm SOI devices show that the deconvolution process significantly improves spatial resolution of time-integrated emission images, pushing their resolution beyond the diffraction limit of Solid Immersion Lenses (SILs).

In this paper, the development of advanced emission data analysis methodologies for IC debugging and characterization is discussed. Techniques for automated layout to emission registration and data segmentations are proposed and demonstrated using both 22 nm and 14 nm SOI test chips. In particular, gate level registration accuracy is leveraged to compare the emission of different types of gates and quickly create variability maps automatically.

The very faint spontaneous near-infrared photon emission of scaled SOI FETs fabricated in 32 nm planar and 14 nm FinFET technologies is characterized and modeled for the first time. A high sensitivity and low noise detector is leveraged to measure emission at low voltages, including sub-threshold and linear regions that are extremely faint. Furthermore, the effect of device threshold is studied and modeled for the first time by comparing the emission from FETs with different Vt.

This paper presents a novel methodology that allows one to reveal SRAM memory content by observing the spontaneous photon emission collected from the backside of the chip. This method is based on our proposed tester-based optical methodology [1] that combines different test patterns, time-integrated and time-resolved emission measurements to localize gates, detect logic states, and identify functional block activity inside a chip in a non-invasive fashion. In this paper, the capability of the technique is demonstrated using a 64 Mb SRAM test chip fabricated in 14 nm SOI technology node. This technique has useful applications for chip debugging, reverse engineering, hardware and software security applications.

Using time-resolved emission to measure electrical signals inside very-large-scale integration complementary metal-oxide-semiconductor circuits in a non-invasive fashion is a very powerful technique. However, node scaling and the related supply voltage reduction have created significant challenges. In this paper, we investigate the limits of established and prototype single photon detectors for future low voltage applications. In particular the performance of a state of the art InGaAs single photon avalanche photodiode and a superconducting single photon detector are reported and compared for low voltage applications using test vehicles fabricated in IBM 65 nm silicon on insulator technologies.

In this paper, we describe the design and the experimental characterization of a packaging technique for backside optical testing of chips requiring wirebonding. Optical testing methods, based either on the collection of spontaneous hot-carrier photoemission or on laser stimulation, require an optical access to the active area of the circuit through the backside of the chip, while still providing mechanical support to the thinned die (very fragile), heat sinking capability, power and electrical signals. The proposed package fulfils all these requirements and it can hence be used for picosecond imaging for circuit analysis/time resolved emission measurements, emission microscopy investigations, laser voltage probe, thermal laser stimulation, photoelectric laser stimulation, and other failure analysis methods that require optical access to the transistor level through the silicon backside. The advantages of the new package are its versatility (it can fit different chip sizes), easy handling, low cost, and the fact that it is designed for optical testing and not just for electrical testing. We successfully used the proposed package for optically test chips in advanced complementary metal-oxide-semiconductor technologies (65 nm): measurements at low voltage are possible thanks to the proposed package.

In this paper, we discuss a set of techniques and analysis methodologies for the reverse engineering and functionality extraction of complex mixed-signal ICs with a special focus for security applications. Front and back side reflected light pattern images at different magnifications are used to identify circuit blocks. Time-integrated and time-resolved photon emission data is used to identify gate logic states, sequences of events, and specific functional activity. Backscattered electron and scanning transmission electron images mosaics are used to reverse engineer individual gates and observe local interconnects. Thermal imaging is used to aid in the functional block identification and analog gates analysis. Different advanced methodologies for tool automation, focusing, mapping, and image processing are also discussed in the context of our proposed electro-optical tester based technique.

Today Superconducting Nanowire Single-Photon Detectors (SNSPDs) are commonly used in different photon-starved applications, including testing and diagnostics of VLSI circuits. Detecting very faint signals in the near-infrared wavelength range requires not only good detection efficiency, but also very low Dark Count Rate (DCR) and jitter. For example, low noise is crucial to enable ultra-low voltage optical testing of integrated circuits. The effect of detector temperature and background thermal radiation on the noise of superconducting single-photon detectors made of NbN meanders is studied in this paper. It is shown that two different regimes can be identified in the DCR vs. bias current characteristics. At high bias, the dark count rate is dominated by the intrinsic noise of the detector, while at low bias current it is dominated by the detection of stray photons that get onto the SNSPD. Changing the detector temperature changes its switching current and only affects the high bias branch of the characteristics: a reduction of the DCR can be achieved by lowering the SNSPD base temperature. On the other hand, changing the temperature of the single-photon light source (e.g. the VLSI circuit under test) only affects the low bias regime: a lower target temperature leads to a smaller DCR.

This work presents a study of the effect of chip temperature on Photon Emission Microscopy (PEM) images acquired with an extended sensitivity near-infrared camera. A detailed analysis of the detection of thermal radiation, as well as leakage and switching signal components will be presented as a function of the camera spectral tailoring. Time-integrated and Time-Resolved Emission (TRE) measurements collected from a 32 nm SOI testchip are used to show that the leakage component is dependent on temperature, while the switching is not. Moreover, the different SNR optimization based on camera spectral tailoring and chip operating temperature is shown for different types of measurements.

We develop a test methodology utilizing the critical path delay to monitor and predict the degradation of circuits during a ramp voltage stress (RVS). Stress is applied by looping functional patterns during RVS. Our results demonstrate that the degradation behavior of a functional circuit can be characterized and analyzed with RVS in a manner similar to that developed for a single transistor. This alternative fast test lends itself to in-line testing with reduced times and small sample numbers.

Self-heating of FinFET devices is a reliability concern, especially for large devices with dense arrays on SOI. In this paper, we leverage the Picosecond time resolution of Time-Resolved Emission (TRE) measurements to quantitatively measure the modulation of the off-state leakage current due to self-heating in individual FinFETs fabricated in SOI technology. This provides the first direct measurement of the self-heating from individual FinFET devices.

We propose a simple, noninvasive, optical technique to measure intra-wafer and intra-chip MOSFET performance variations. Technique utilizes correlation between device performance and weak near-infrared emission from its off-state current. It maps performance variations, producing quantitative data. We experimentally demonstrate our technique on 130 nm SOI microprocessor.

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

This work presents a comparison of two generations of Superconducting nanowire Single-Photon Detector (SnSPD) prototypes used for Time-Resolved Emission (TRE) measurements from VLSI chips. The performance of the systems is compared in order to understand the figures of merit that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for ultra-low voltage applications. We will show that measurements down to a new World record low 0.4 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform SNR.

In this paper, we present the latest results obtained with a 2D Picosecond Imaging Circuit Analysis (PICA) camera with enhanced Near InfraRed (NIR) sensitivity [1] for taking 2D Time Resolved Emission (TRE). We will discuss key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the interpretation of the failure signatures of several VLSI chips. Besides conventional chip diagnostics, specific focus will be dedicated to new areas of applications, such as security and reverse engineering [2]. We will also discuss spectral analysis and other techniques that can be used to extract valuable information from the PICA dataset.

This paper presents a comprehensive study of the impact of Hot Carrier Injection (HCI) on differential LC Voltage Controlled Oscillator (VCO) reliability tests. Although Negative Bias Temperature Instability (NBTI) has been recognized as major cause for reliability degradation of advanced circuits, HCI-induced degradation may become significant due to the accelerated aging of reliability tests leading to incorrect circuit lifetime prediction. To distinguish HCI effects, different stress voltages and frequencies are applied in Constant Voltage Stress (CVS) and Ramp Voltage Stress (RVS) tests. It is verified that the stress voltage and frequency dependence of time and voltage exponents in the reliability tests are due to the effect of HCI. Based on the observed results, a methodology is proposed to define proper stress conditions for accelerated circuit reliability tests for better lifetime prediction.

This paper presents a novel methodology for hardware security and Trojan detection applications. The method is based on our proposed tester-based optical methodology that combines different test patterns, time-integrated and time-resolved emission measurements to localize gates, detect logic states, and identify functional block activity inside a chip in a non-invasive fashion. A detailed application example using a 90 nm bulk digital test chip shows that emission images can be effectively used to identify unexpected and missing emission signatures that may be related to chip alterations.

This paper presents a novel and powerful methodology for extracting functional blocks in hardware security and Trojan detection applications. The method is based on our proposed tester-based optical methodology that combines different test patterns, time-integrated and time-resolved emission measurements to identify and localize logic state changes and functional block activity inside a chip in a non invasive fashion. Detailed examples using a mixed-signal chip are presented and discussed to explain our proposed method.

This paper describes the strategies and techniques used to diagnose failures in the IBM 600-MHz S/390® G5 (Generation 5) CMOS microprocessor and the associated cache chips. The complexity, density, cycle time, and technology issues related to the hardware, coupled with time-to-market requirements, have necessitated a quick diagnostic turnaround time. Beginning with the first prototype of the G5 microprocessor chip, intense chip diagnostics and physical failure analysis (PFA) have successfully identified the root causes of many failures, including process, design, and random manufacturing defects. In this paper, three different diagnostic techniques are described that have enabled the G5 to achieve its objective. An example is presented for each technique to demonstrate its effectiveness.

The paper introduces fundamental principles for design of position and force (P/F) controllers. There are two principles guiding the design of a P/F controller: (i) the principle of invariancy; and (ii) the principle of consistency. The principle of invariancy serves as a guideline for the decomposition of the task space into force and position subspaces. The principle of consistency relates the free motion and constrained force to the characteristics of the environment. This principle guarantees the overall stability and the reduction of interactions between the position and force subcontrollers. Based on these two principles, a theoretical framework for design and analysis of P/F controllers is established, and a generic P/F controller is proposed. The proposed P/F controller and other generic P/F controllers are compared in terms of stability and interactions between the two subcontrollers.

We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications

In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.

In this paper, a methodology for robot position/force controller design is discussed. Unlike pure position controllers for robotic manipulators, the position/force controller consists of two parts: position and force subcontrollers. The principle of consistence, as a guideline for design of position /force controllers, is proposed, which requires that both sub-controllers not interact with each other. A systematic approach, based on the principle of consistency, is submitted to be a platform for the design of position/force controllers.

In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.

In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the problem. In addition, we will show how high resolution mapping of the Light Emission from Off-State Leakage Current (LEOSLC) from the chip was instrumental in leading the investigative effort to the right root cause. The problem was successfully traced to a p-FET used for IDDQ measurement during manufacturing test that caused an undesirable coupling path. Fortunately this specific configuration was unique to this particular design and was easy to fix with a single mask change.

The Semiconductor Industry Associates (SIA) estimates that counterfeiting costs the US semiconductor companies $7.5B in lost revenue, and this is indeed a growing global problem. Repackaging the old ICs, selling the failed test parts, as well as gray marketing, are the most dominant counterfeiting practices. Can technology do a better job than lawyers? What are the technical challenges to be addressed? What EDA technologies will work: embedding IP protection measures in the design phase, developing rapid post- silicon certification, or counterfeit detection tools and methods?

This paper details tester-based optical and electrical diagnostic system and techniques that aim at diagnosing various types of problems that exist in today's VLSI chips, especially during initial bring-up stage. The versatility of the electrical test creates flexible test controls while optical diagnostic tools, such as emission-based systems, provide a deep understanding of what is going on inside the chip. Tightly integrating both methods produces a powerful diagnostic system and it also opens a door for creating a series of new diagnostic techniques for resolving new families of problems as illustrated in this paper with several examples.

This paper presents, for the first time, near-infrared spectral photon emission measurements of a ring oscillator in IBM's 45 nm SOI process technology. The setup employs a cryogenically cooled MCT camera and different band-pass filters with a very broad spectral range from 850–2100 nm. The paper presents the spectral data, discusses the thermal contributions, and analyzes its impact for selecting appropriate detectors and tools for time-resolved measurements in present and future technology nodes.