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Hybrid bonding, with wafer-level bonding to form oxide-oxide bonds and Cu-Cu bonds, is a promising technology for 3D integrated circuits. In this study, we describe the design, processing. and characterization of test structures formed using hybrid bonding for wafers built in two different technologies; a 180 nm Al BEOL technology and a 110nm Cu BEOL technology. The reliability evaluation shows good results for package level and wafer level stresses.

Self-aligned metal capping layers formed by electroless plating, such as CoWP and NiMoP, are being investigated for a number of Cu interconnect technologies. One application is for high performance logic chips at the 45nm node and below. The main motivation for using these capping layers is to improve electromigration lifetime, and a dielectric cap is typically used in addition to the metal cap. An improvement in electromigration lifetime of over 100X is observed with a CoWP cap, and the lifetime is independent of the direction of electron flow for dual damascene structures. A different application is for CMOS image sensors using 0.18@mm technology. For this application, the self-aligned metal cap replaces the dielectric cap, resulting in improved optical performance of the image sensor. The uniformity of the CoWP is critical for this application; if there are thin regions in the capping layer, the Cu will be exposed to the etch or strip chemistry, and via yield and reliability will be poor. For both applications the main issue with using selective capping layers is loss of selectivity, which results in high leakage currents between the metal lines. Interestingly, the leakage can actually be lower for a stand-alone CoWP cap compared to a stand-alone SiN cap, presumably due to damage associated with the SiN deposition.

Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI technologies have been improved to follow the evolving system requirements for insertion loss, isolation, voltage tolerance, linearity, integration and cost. In this paper, the performance results of the latest generations of RF SOI switch technologies from IBM are reviewed and technology elements that contribute to improved performance are discussed. Future improvements are also discussed.

Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to minimize wafer-to-wafer variations in the Al linewidth.

Thin silicon die (100 um or less) are required for a number of applications, including stacked die packages and three-dimensional integrated circuits (3D-IC). The wafer thinning process is conceptually simple, but requires optimization of the backside finish and dicing to ensure high die strength. High die strength is required to minimize yield loss during assembly and to ensure high reliability during device operation. In this paper, we describe process optimization for thin wafers and thin die, and how these processes affect the fracture strength of silicon.

A manufacturable 130nm SiGe BiCMOS RF technology for high-performance mm-wave analog applications having a high-speed SiGe Heterojunction Bipolar Transistor (HBT) integrated into a full-featured RFCMOS is presented. The technology features a high performance (HP) SiGe HBT with fT/fMAX of 260/320 GHz, a high breakdown (HB) HBT with BVCEO of 3.5V, 130nm RF CMOS, and a full suite of passive devices. Specific device results pertaining to this BiCMOS8XP technology are discussed in this paper.

The thermal resistances of thirty-nine different back end of line (BEOL) test sites consisting of four line levels and three via levels in SiCOH were measured. The measured unit resistance values ranged from 0.5 to 5.5 C-mm2/W. The percent via area was varied from 0.31 to 6.25 %, the percent line area from 17 to 67%, the configuration of the vias, the distance between vias, and the line and via pitch were also varied. The measured values were compared to results from an internally developed electromagnetic simulation tool, ChipJoule. Comparison of the simulations with measured values validated the ChipJoule tool, which can be used to simulate full BEOL structures using mask design data.

Silicides are widely used in silicon integrated circuits as contacts and interconnections. In many applications silicides are used on polycrystalline silicon (polysilicon) such as the gates of FETs and the emitter of bipolar transistors. The use of silicide on polysilicon structures presents a number of unique challenges both in formation of the silicide and in morphological stability during high temperature processing. The purpose of this paper is to review the formation, morphology, and thermal stability of silicides on polysilicon. Mechanisms for silicide roughening on polysilicon are discussed including non-uniform initial reactions, agglomeration, and silicide enhanced grain growth. Results for silicides on polysilicon are compared with those on single crystal Si where relevant, A detailed description of silicide instability and device degradation is presented for a number of silicides, emphasizing TiSi 2 , CoSi 2 , and WSi 2 . Finally, methods for improving the stability of silicides on polysilicon are discussed.

During technology development, the study of low-k TDDB is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this study, we conducted several important experiments including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by liner-free interconnect build, 3D on-flight stress-induced leakage current (SILC) measurement, triangular voltage sweep (TVS) versus TDDB, and Cu-free interconnect build at 32nm to experimentally confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model.

On-chip copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects [1]. Initially, copper interconnects were only used for high performance logic circuits. However, Cu interconnects are now used in a wide variety of integrated circuits, including dynamic random access memories (DRAM) [2], RF circuits [3], and CMOS image sensors [4]. Copper interconnects will continue to be used for the 32 and 22nm technology nodes. However, there are many challenges with implementation of Cu interconnects at these nodes, including increased resistivity, integration with porous low-k materials, and reliability. In addition, for RF circuits, integration of passive devices is required. In this paper, each of these topics is addressed.

We have developed a process for fabricating thin W films for local interconnect applications in circuits using Si bipolar transistors. Tungsten films deposited by both sputtering and chemical vapor deposition (CVD) methods were patterned over topography with a highly anisotropic and selective single-wafer reactive ion etch (RIE) process in Cl 2 , and O 2 . Maze structures were tested electrically to characterize the opens and shorts yield. In addition, the profiles of etched lines were characterized by cross-sectional scanning electron microscopy. High yields (>80%) were obtained for a wide range of RIE conditions on mazes of variable pitch (minimum 1.8 μm) with lengths >0.5 m

Junction leakage has been observed for shallow diodes that simulate emitter-base junctions in npn bipolar transistors, due to CoSi 2 formation on As-doped polysilicon. The leakage depends on the Co thickness, the polysilicon thickness, and the device area, but is relatively independent of the Co anneal conditions between 600 and 800 o C. Severe roughness at the CoSi 2 -polysilicon interface is also observed, especially after annealing at 800 o C. The leakage is probably due to CoSi 2 protrusions in the substrate that are produced during the initial silicide formation

We have studied the properties of reactively sputtered TiN films used as diffusion barriers for Al‐Cu metallization in submicron bipolar transistors. Emitter‐base diodes with shallow junctions were fabricated to monitor the integrity of the barrier via junction leakage measurements. Scanning and transmission electron microscopy were used to study the morphology and step coverage of these films, and also for barrier failure analysis. The effectiveness of the barrier depends on both the nominal thickness of the TiN layer and on the device dimensions. For thin TiN layers (∼47 nm), high junction leakage was observed on narrow emitters (0.5 μm) but not on wide emitters (5 μm). These observations highlight the reliability and yield concerns associated with the use of sputtered TiN films for deep submicron technologies. In some cases, low‐temperature (500 °C) epitaxial alignment of the emitter polysilicon was observed, associated with Al penetration of the barrier. This indicates that the Al provides an enhancement of the tendency towards epitaxial alignment of the polysilicon grains. For thicker TiN layers (∼83 nm), low leakage was observed on both narrow and wide emitters, and no unusual epitaxial alignment was observed.

With a prevalence rising with age from 0.05% at age 25-35 years to more than 5% among people aged 69 years or more, atrial fibrillation (AF) and in general atrial tachyarrhythmias (AT) are now the single most common sustained arrhythmia [1]. Once considered a benign disease, AF is increasingly being recognized as a significant cause of morbidity and mortality. AT can be treated by a vast array of pharmaceutical and nonpharmacological therapies, suggest­ing that no single treatment is sufficiently simple, successful, and cheap to exclude other therapies. Many new therapies are presently being developed, among which are electrical therapies designed to prevent and convert AT. Clinical experience indicates that monotherapeutic approaches (drug, abla­tion, or device) are often associated with unsatisfactory results in the treat­ment of AT patients [1-12]. Because all therapies have poor efficacy when con­sidered alone, interest in the role of combinations of therapies (hybrid thera­py) has recently increased. The rationale underlying hybrid therapy is that a combination of modalities of intervention in AT might have a synergistic effect, with the efficacy of each intervention building upon that of the others [12]. At present this concept is being considered particularly in the prevention of AT recurrence, but hybrid therapy has also been utilized both in facilitating restoration to sinus rhythm and in control of heart rate.

As VLSI back end of line (BEOL) wiring is scaled to 0.175 /spl mu/m dimensions and sub-0.5 /spl mu/m pitches, the challenges to conventional Al RIE BEOL processes are the etching and the reliability of tall/narrow Al lines and the oxide gap fill and planarization of such lines. Dual damascene approaches for gigascale DRAM BEOL offer advantages over conventional schemes of self planarization and simple etches. Al damascene has advantages compared to Cu damascene of being more compatible with previous technologies, limited contamination issues, cost effectiveness and filling of smaller line width/larger aspect ratio structures. However, an Al damascene approach requires advanced Al filling capabilities. In this paper, we compare the Al filling of 0.25 to 0.175 /spl mu/m/0.5 to 0.35 /spl mu/m pitch, 3.0 to 5 to 1 aspect ratio structures with a reflow Al process and a CVD/PVD Al processes. We show that a CVD/PVD Al fill process produces good electrical and reliability performance down to 0.175 /spl mu/m ground rules, while a conventional reflow Al process is potentially limited to 0.25 /spl mu/m ground rule devices. We also show that the electromigration lifetime of CVD/PVD Al damascene is far superior to that of Al RIE, alleviating the need to use Cu damascene for improved reliability. Thus, we believe that the CVD/PVD Al fill process is viable for 1 Gb dual damascene metallization schemes at least down to 0.175 /spl mu/m structures/0.35 /spl mu/m pitches and 5 to 1 aspect ratios.

Impedance and modulation spectroscopy techniques were used to characterize the damage to Si promoted by reactive ion etching (RIE). We compare in this paper our previous results on liquid junction interfaces with Schottky barrier device configurations Ti/Si and Al/Si and metal‐oxide semiconductors Al/SiO2/Si. Important device parameters, such as the barrier height, obtained from the impedance data will be compared with current‐voltage measurements. The results cannot be explained only by considering the thermionic emission theory. For the CHF3/Ar and CF4 RIE treatments, the observed barrier lowering confirms our results with liquid junctions, supporting the existence of positive charges on the surface of the damaged Si. For the CClF3/H2 RIE treatment the results are consistent with the existence of a porous polymer layer on the semiconductor surface. In terms of sensitivity of the dielectric properties to the RIE treatment, the liquid junction is the most sensitive, followed by SB devices, with the MOS co...