Search

Bipolar transistors of high cut off frequency ( f_{T}=9 GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.

This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.

A Self-aligning Polysilicon ELectrode technology (SPEL) is proposed to realize future high performance LSIs. This technology, based on a preferential dry etching of a highly doped polysilicon, makes it possible to halve the contact region areas of MOS and bipolar transistors as compared to conventional ones. Additionally, reduction of parasitic capacitance and resistance are demonstrated for the former transistors.

A novel scaled down high resistor (1µm or less in length) for future static RAMs was realized by using the slow arsenic diffusion in oxygen implanted polysilicon, where arsenic is partially doped to form polysilicon interconnection layer. The current voltage characteristics of the oxygen doped polysilicon resistors were almost linear, and the marked decrease in resistance for higher applied voltage, observed in non-doped polysilicon, could not be found. Moreover the field effect modulation of the resistance in the oxygen doped polysilicon was much less than that of non-doped one. Applicability of the scaled down oxygen implanted polysilicon resistor was thus demonstrated for future static RAMs.

A high breakdown voltage for a planar junction has been achieved by using a layer of oxygen doped amorphous silicon film over a composite of chemical-vapour deposition (CVD) phosphosilicate glass (PSG) film, CVD SiO2 film, and thermally oxidised SiO2. The high breakdown phenomenon was analysed from the viewpoint of surface depletion layer width. Measurements of the surface depletion layer width by scanning laser microscope, and numerical calculations of a 2-dimensional Poisson's equation for the distributed potential in oxygen doped amorphous silicon showed close agreement. The distributed potential of oxygen doped amorphous silicon influenced induction of the surface depletion layer, resulting in a reduced surface electric field and higher breakdown voltage. The leakage current of oxygen doped amorphous silicon was negligible at high temperatures (>125°C) compared to the normal junction leakage current. This was due to the low activation energy of conductivity for oxygen doped amorphous silicon.