1. Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration
- Author
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Hassan Mostafa, Michael H. Zakhari, Mohamed A. Abd El Ghany, Mohamed A. Elgammal, Heba Elhosary, Khaled A. Helal Kelany, and Khaled Nabil Salama
- Subjects
General Computer Science ,Computer science ,02 engineering and technology ,03 medical and health sciences ,0302 clinical medicine ,Application-specific integrated circuit ,sequential minimal optimization (SMO) ,Low power ,0202 electrical engineering, electronic engineering, information engineering ,General Materials Science ,Sensitivity (control systems) ,Field-programmable gate array ,business.industry ,feature extraction ,020208 electrical & electronic engineering ,General Engineering ,Control reconfiguration ,TK1-9971 ,accelerator IP ,Support vector machine ,classification ,CMOS ,Sequential minimal optimization ,Hardware acceleration ,support vector machine (SVM) ,Electrical engineering. Electronics. Nuclear engineering ,business ,030217 neurology & neurosurgery ,Computer hardware - Abstract
In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.
- Published
- 2021
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