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Due to the increasing integration of renewable energies into the distribution grid, a deterioration of the grid power quality is expected. Consisting of a low-frequency transformer and a fractionally rated power electronic converter, hybrid transformers (HTs) can be applied to ensure a high power quality by controlling voltage, active and reactive power dynamically. For the application in conventional grids, HTs have to withstand considerable overvoltages and overcurrents during voltage surges or short circuits. Although HTs recently gained increasing research interest, protection requirements and protection concepts have not been discussed yet. These aspects are, however, essential to evaluate the practical potential of HTs. In this article, protection requirements are derived and a protection concept is developed and verified by simulations and experiments for a 100-kVA hybrid distribution transformer. Although the protection concept has a considerable impact on the design and performance of the converter, it increases the total losses and volume of the HT only insignificantly. An efficiency of 98.48% is achievable for an HT including protection, which is only slightly lower than the efficiency of 98.64% for a comparable conventional transformer. This renders the HT a promising solution for today's and future ac grids.

In this paper, the efficiency of the CLIC solid-state pulse modulator developed for the CERN research center and the long-pulse modulator system built for the ESS facility is investigated in detail. The analysis shows the current efficiency status of the modulators and how their performance could be improved by using SiC devices., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

Using GaN HEMTs in high current applications, such as pulsed power modulators for particle accelerator systems, requires the parallelization of multiple devices. In order to achieve a dynamically balanced current distribution between the parallel devices, synchronized gate voltages are crucial. Furthermore, the high switching speeds, which are often required in pulsed power systems, requires a high driving current capability and fast rise/fall times of the gate driver. Therefore, this paper presents a gate driver, based on a low voltage GaN HEMT half bridge, for driving four paralleled 650 V e-mode GaN HEMTs in a low inductive switching cell design., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

Stacked Polyphase Bridge Converters (SPB-C) are well suited for integrated motor drives, i.e. for systems that combine an electric motor with its supplying power electronic converter in one compact unit. A SPB-C requires a motor with multiple 3-phase winding systems. In the literature, the SPB-C is typically combined with motors whose winding systems are phase-aligned. This type of winding is magnetically equivalent to a 3-phase winding (with parallel branches). In this paper, the SPB-C with either 2, 3, or 4 modules is combined with a motor that has non-phase-aligned winding systems what results in a 6-, a 9-, or a 12-phase system, respectively. These multiphase systems are compared to 3-phase systems with the same number of modules with regard to efficiency, power density, and the possible degree of modularity and the benefits of the multiphase systems are evaluated., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

In hybrid DC circuit breakers with current-injection, the arc in the mechanical switch is extinguished with a current pulse. After the arc extinction, the voltage increase across the mechanical switch must be limited in order to avoid an arc reignition. The voltage across the MS is usually assumed to be equal to the voltage across the capacitor CCI in the current-injection circuit, which increases slowly due to slow charging of the capacitor by the fault current. However, in reality the voltage across capacitor CCI is usually not zero at the point in time of the arc extinction. This results in high transient voltages across the mechanical switch, the so called so-called initial transient interruption voltage (ITIV) after the arc extinguishes. However, a fast increasing ITIV can lead to a thermal reignition of the arc. Therefore, it is crucial for the design of a DC-CB to understand, which effects contribute to a high ITIV. In this paper, these causes and the influence of the ITIV are investigated. Furthermore, the beneficial influence of grading capacitors parallel to the MS is investigated. Finally, an optimization of a DC-CB including the ITIV and its results are presented for a typical implementation of a current-injection DC-CB., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

For small scale roof-top systems, there is a trend towards module-integrated electronics. Module integrated ac inverters (ac modules) connect each photovoltaic (PV) module separately to the single-phase grid. They feature not only increased yield due to module-level maximum power point (MPP) tracking, but also further advantages such as reduced installation cost. This work investigates the concept of subpanel-level MPP tracking for ac modules, which allows us to increase yield thanks to reduced mismatching losses. Topology concepts to realize such a converter are systematically investigated and categorized. A topology comparison identifies two promising system concepts: first a single-stage converter with a three-port power balancer and second a two-stage topology with three paralleled dc–dc converters and a pulse width modulation full bridge. The later features the advantage of a small power-decoupling capacitor and is therefore further investigated. A model-based optimization of the investigated multi-input ac module is performed, applying high performing Gallium Nitride (GaN) devices and nanocrystalline core materials to increase efficiency. The built prototype confirms the accuracy of the model-based optimization. The performed efficiency study reveals an achievable efficiency of $\eta _{\text{EU}}$ = 94.5%. In order to compete with single-input ac modules, achieving typically an efficiency of 95.5%, the efficiency of multi-input ac modules must improve beyond the level achieved with the investigated two-stage ac-module topology. Given this result, the alternative system concept with a three-port power balancer in combination with a single-stage converter seems to be more promising, as it is conceptually similar to the high efficient single-input ac modules and may achieve the same high efficiency.

This paper presents a novel real-time implementation of linear model predictive control (MPC) schemes based on region-less explicit MPC (RL-EMPC). RL-EMPC is a recently proposed explicit MPC solution for achieving a low memory footprint compared to other explicit MPC methods. Thus RL-EMPC can effectively handle systems with high sampling rates even for large-size MPC problems, i.e. systems with many states and/or constraints. An architecture for an implementation on an FPGA device is presented and validated with two application examples (buck-boost converter, modular multilevel converter). Simulation results on FPGA hardware-level demonstrate that long-horizon linear MPC can be implemented on low-cost FPGAs with the proposed architecture for various power electronic systems., IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society, ISBN:978-1-7281-5414-5, ISBN:978-1-7281-5413-8, ISBN:978-1-7281-5415-2

The required module capacitance value is a driving factor of the volume and cost of modular multilevel converters (MMC). In order to minimize the required capacitance value, an optimal circulating current and common mode (CM) voltage injection strategy which keeps the conduction losses and die CM voltage as low as possible is proposed in this paper. Unlike previous methods from literature that only focus on minimizing the amplitude of energy fluctuation in the arm capacitors, the proposed optimization procedure is based on the optimal shaping of both the arm voltages and energies. As a result, the proposed optimization scheme achieves a further reduction in the required capacitance value of up to 42% compared to existing methods. The procedure is validated with closed loop simulation results covering the full operating range of an exemplary MMC., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

In this paper, a novel feedback controller concept for grid-connected Modular Multilevel Converters (MMC) is proposed. The controller is based on the Linear Quadratic Regulator (LQR) method and shows outstanding control performance since it is a multi-input multi-output (MIMO) controller. The proposed controller achieves efficient energy balancing control with high bandwidth, such that the required margin for the module capacitance value for dynamic control is reduced and an excellent transient behavior can be accomplished. Alternatively, compact MMC designs can be realized with a reduced capacitance value by sacrificing some transient performance. The implementation requires a relatively low computational effort, and the simple control structure enables a straightforward tuning and time-delay compensation., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

Advanced high voltage (3.3-15kV) SiC MOSFETs have been developed for future medium voltage converters over the past decade due to their superior performance. In order to better understand the operation limits and potential of these devices, this paper evaluates the I max -f sw -dv/dt trade-off (maximal current-handling capability at a specific switching frequency and at a defined switching speed) for high voltage SiC MOSFETs based on a proposed linearized analytical switching loss model. There, high voltage SiC MOSFETs manufactured by Cree combined with data from literature for scaling are used as reference.

Birefringence and optical losses in the optical sensor head of a Faraday effect based, high accuracy and high bandwidth current measurement system lead to changes of the polarisation state and orientation. These changes, if not properly determined and calibrated, lead to systematic measurement errors. Therefore, a calibration method for the optical current measurement system focusing on pulse current applications is proposed. The procedure is based on a zero-current measurement and a full (Stokes) polarimeter. It determines the full polarisation state and orientation of a beam propagating through the optical system. The calibration method then allows to determine the parasitic linear birefringence caused by any subsequent optical element in the system. Eventually, an error analysis characterising the potential error reduction by the proposed calibration method is conducted. Further, the additionally introduced error sources caused by the full polarimeter approach are characterised., 2020 22nd European Conference on Power Electronics and Applications (EPE'20 ECCE Europe), ISBN:978-9-0758-1536-8, ISBN:978-1-7281-9807-1

Excellent control performance is a prerequisite to operate compact modular multilevel converter (MMC) designs that employ very small module capacitance values. This paper presents a novel model predictive control (MPC) scheme featuring a linear and accurate prediction model to overcome the drawbacks of comparable control schemes. The MPC is based on a modulator that determines the switching states of the individual modules to guarantee scalability of the algorithm also for MMCs with a high number of modules. The control performance of the proposed MPC scheme is evaluated with simulations and compared to a classic cascaded PI-controller scheme., IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, ISBN:978-1-7281-4878-6, ISBN:978-1-7281-4879-3

Low switching energies render GaN semiconductor switches a promising technology for hard-switched inverters. For high current applications, the parallel connection of multiple GaN devices makes the PCB and gate drive design challenging. Furthermore, the SMD packages of currently available GaN devices exacerbate a mechanically robust and at the same time thermally and electrically highly conductive integration of the switches into the overall converter. This paper quantifies the performance improvements of GaN FETs over Si MOSFETs and investigates implications of paralleling GaN on the gate drive design. Based on a low voltage high current GaN half-bridge cell, $\frac{{{\text{d}}v}}{{{\text{d}}t}}$-induced turn-on and oscillations of parallel switches are evaluated theoretically and experimentally. Design recommendations for the gate drive and the integration of such a cell into the overall converter are presented.

This paper presents the design of the optical system of a current sensor with a wide bandwidth and a high accuracy. The principle is based on the Faraday effect, which describes the effect of magnetic fields on linearly polarized light in magneto-optical material. To identify suitable materials for the optical system the main requirements and specification are determined. A theoretical description of the optical system shows a maximal applicable magnetic field frequency due to the finite velocity of light inside the material. Hence, the theoretical characterisation of the system implies practical boundaries on the optical material and its specifications. Finally, two different magneto-optical crystals, Terbium Gallium Garnet and Cadmium Manganese Telluride, are investigated, assembled and put into an optical system prototype.

Circuit breakers with current injection enable fast interruption of fault currents in DC grids. Independent of the topology, a high number of semiconductors and capacitors is required. The minimum required number of semiconductors and capacitors depend mainly on the system voltage and the maximum fault current. However, also the MS characteristics have considerable influence on the required number of semiconductors and capacitors. Therefore, in this paper the influence of the MS characteristics on the arc extinction and the influence of the arc voltage on the DC-CB design is presented. In addition, optimization procedures for current injection circuit breaker are presented, which include the MS characteristics and four different possibilities to include the arc voltage. Finally, three DC-CB topologies are compared in terms of number of semiconductors and capacitors., 2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe), ISBN:978-9-0758-1531-3, ISBN:978-9-0758-1530-6, ISBN:978-1-7281-2361-5

The growing need for higher efficiency in converter systems and in power electronic systems in general has led to the implementation of more complex and sophisticated control algorithms. Often, the controller unit is separated from the sensors and the data has to be transmitted via an isolated channel. Plastic optical fibers are utilized for this task due to their low cost, high robustness and easy handling. In order to reduce the number of fibers, intensity modulation can be used to transmit multiple signals over a single optical fiber. A recently introduced modulation scheme with an additional intensity level indicating the clock allows a simple clock recovery at the receiver. In this paper, three receiver concepts based on this modulation scheme are presented for medium data rates in the range of 20 - 50 Mbps which is sufficient for most power electronic applications. The low complexity and small footprint of the proposed concepts facilitate the system integration. Furthermore, a more compact system can be designed due to the lower number of necessary fibers and corresponding transmitter and receiver circuits., 2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe), ISBN:978-9-0758-1531-3, ISBN:978-9-0758-1530-6, ISBN:978-1-7281-2361-5

Hardware-in-the-Loop tests of components for high-voltage dc transmission grids, for example circuit breakers, require converter systems capable of generating a high output current with fast transients of the output signal at different output voltages. In this paper, a three-level buck converter (N3L) employing three different supply voltages to enable a wide voltage operation range is presented. The modulation of the converter is investigated in detail with special focus on ripple cancellation, the startup of the interleaved converter and the level shifting between different converter output voltages. A prototype system is designed and constructed, optimized for pulsed power operation and compared to a two level and to a neutral point clamped converter design. The system has been simulated numerically and the design boundaries are validated by measurements on the prototype system.

IEEE Transactions on Industrial Electronics, 66 (3), ISSN:0278-0046, ISSN:1557-9948

IEEJ Transactions on Industry Applications, 8 (2), ISSN:1348-8163, ISSN:0913-6339

Hybrid transformers (HT) are a promising concept to increase the grid flexibility. In the past, only HT with bidirectional auxiliary converter have been investigated. In this paper, HT with unidirectional auxiliary converter, which are advantageous in terms of reliability, cost and complexity, are investigated and their operational limits are derived., 2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe), ISBN:978-9-0758-1531-3, ISBN:978-9-0758-1530-6, ISBN:978-1-7281-2361-5

The double-star chopper-cell (DSCC) and the double-star bridge-cell (DSBC) modular multilevel converters (MMCs) may be designed with a reduced number of modules when higher grid currents and an increased volume of the passive components are acceptable. The full-bridge modules in the DSBC even allow for designs with increased power conversion efficiency at the expense of additional modules. This paper presents an integrated optimal design methodology that exploits these additional degrees of freedom while at the same time maximizing power density and power conversion efficiency. To demonstrate the effectiveness of the proposed approach, a short-circuit-proof 250kW, 35kVDC bidirectional active rectifier prototype system is presented that has been designed with emphasis on reduced realization effort.

2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia), ISBN:978-4-88686-405-5, ISBN:978-4-88686-403-1, ISBN:978-1-5386-4190-3

2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia), ISBN:978-4-88686-405-5, ISBN:978-4-88686-403-1, ISBN:978-1-5386-4190-3

The calculation of eddy current losses in foil windings exposed to a 2-D fringing field is a complex task because of the current displacement along the height of the foil. For model-based optimization of magnetic components, loss calculation with 2-D finite element method simulation is not an option because of the high computational effort. The existing alternative calculation methods with low computational effort, rely on approximations applicable only to a certain geometrical arrangement of the windings and the air gap. Therefore, in this study, a new semi-numerical method was developed to overcome these limitations. The method is based on the mirroring method and is applicable to arbitrary air gaps and winding arrangements. The accuracy of the new method was verified by measurements, and the deviation of the model results from the measured losses was found to be below 15%.

In this paper, the results of a 2.88 MW solid state long pulse modulator, which has been designed for the new linear collider at the european spallation source in Lund, are summarized. The presented modulator generates an output voltage pulse of 115 kV with a pulse length of 3.5 ms. The modulator design is verified by measurements performed with a full scale prototype, which is operated under nominal load conditions. All specifications are well within the given limits and the system achieves a pulse efficiency of 96.78% and an overall system efficiency of 91.88%.

Electronic ballasts for high-pressure sodium lamps based on an ac-chopper topology are proposed as a cheaper and less complex alternative to the industry-standard low-frequency square-wave ballasts. In this paper, the design process of the ac-chopper ballast is reviewed, and the design tradeoffs caused by the single-stage topology are discussed. The analytical and simulation results are verified with measurements of a 250-W prototype system, including a detailed list of the losses for the different circuit components and electromagnetic compatibility measurements. Due to the disadvantages of the single-stage topology, a comparison to a two-stage ballast using the inverter stage of the ac-chopper ballast with a separate power factor correction stage is provided.

Switching devices based on SiC offer outstanding performance with respect to operating frequency, junction temperature, and conduction losses enabling significant improvement of the performance of converter systems. There, the cascode consisting of a MOSFET and a JFET has additionally the advantage of being a normally off device and offering a simple control via the gate of the MOSFET. Without dv /dt-control, however, the transients for hard commutation reach values of up to 45kV/μs, which could lead to electromagnetic interference problems. Especially in drive systems, problems could occur, which are related to earth currents (bearing currents) due to parasitic capacitances. Therefore, new dv/d t-control methods for the SiC JFET/Si MOSFET cascode as well as measurement results are presented in this paper. Based on this new concepts, the outstanding performance of the SiC devices can be fully utilized without impairing electromagnetic compatibility.

PFC converters are widely used in industrial drive systems. The modulation scheme and the topology of the converter have a considerable impact not only on the switching losses, but also on the volume of the passive components, i.e. the EMI filter (CM and DM) and the dC link capacitors. In order to evaluate this impact, different modulation schemes for 2L and 3L topologies are analysed in this paper based on comprehensive converter optimizations. In these optimizations also a model for the EMI filter is included and the optimal converter volume including the EMI filter is evaluated for the different topologies and modulation schemes. Thus, significant differences in the converter volume can be observed for the different modulation schemes. Also the impact of SiC semiconductors on the system performance is analysed. The 3L-NPB modulation scheme with a NPC topology offers the best compromise of heat sink, EMI filter and DC link capacitor volume., 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), ISBN:978-90-75815-27-6, ISBN:978-90-75815-26-9, ISBN:978-1-5386-0530-1

2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), ISBN:978-9-0758-1527-6, ISBN:978-90-75815-26-9, ISBN:978-1-5386-0530-1

Recently, modular multilevel conterters (MMC) are also considered for medium voltage (MV) applications, where the number of modules and the switching frequency are relatively low compared to high voltage (HV) applications. In this context, standard modulation methods can cause relatively large output voltage errors. This effect is amplified even more, if the value of the module capacitances is decreased to reduce cost and volume of the MMC. Large output voltage errors disturb the higher level closed loop control of the MMC significantly, such that control targets (e.g. keeping the circulating current zero) could not be met anymore. This paper analyses the output voltage error induced by the standard level shifted PWM method and proposes three approaches to reduce the error. All four methods are compared with respect to the error for different switching frequencies and arm currents. The effects on the closed loop performance of a current controller are investigated with time domain simulations., 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), ISBN:978-907581527-6, ISBN:978-90-75815-26-9, ISBN:978-1-5386-0530-1

Large inrush currents can occur when power transformers are connected to the grid. In the past, a wide range of countermeasures has been developed whereof the application of power electronic converters recently received more attention. With hybrid transformers combining a conventional transformer with a power electronic converter, the elimination of inrush currents can be realized without considerable additional hardware effort. For such hybrid transformers, a novel mitigation procedure is proposed, which is based on the injection of a synchronous core flux before the transformer is connected to the grid. In addition, dedicated demagnetization strategies applicable for grid connected converters with filter elements are presented. The effectiveness of the proposed procedure is verified by comprehensive simulations and a comparison to a conventional method., 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), ISBN:978-90-75815-27-6, ISBN:978-90-75815-26-9, ISBN:978-1-5386-0530-1

For Dual Active Bridge (DAB) converters a large number of modulation schemes exist, which allow to operate the converter in a wide voltage/power range at a very high efficiency. However, the implementation of these modulation schemes and the transition between the schemes during transient conditions is relatively complicated. Therefore, a simple and flexible concept for generating the PWM signals of the eight switches for all possible modulation schemes and also transient conditions is presented in this paper. The concept is validated by Simulink/Plecs co-simulations for a single module of interleaved DC-DC converter system designed as a battery interface for high power drive systems., 2017 19th European Conference on Power Electronics and Applications (EPE'17 ECCE Europe), ISBN:978-90-75815-27-6, ISBN:978-90-75815-26-9, ISBN:978-1-5386-0530-1

2016 18th European Conference on Power Electronics and Applications (EPE'16 ECCE Europe), ISBN:978-9-0758-1524-5, ISBN:978-1-5090-1410-1

The benefits of modular multilevel converters come at a price: Their high level of complexity demands for an intricate design methodology and a sophisticated control structure. This is especially true for converters that need to be able to recover from short-circuits, grid faults, communication faults or module faults. In order to build a reliable system, it is thus important to understand the effect that the control structure has on the converter design. When protecting each module against over-voltages and overcurrents individually, the performance of the central controller is no longer immediately safety critical. This allows to communicate the switching times and measurements with a daisy-chain-like communication architecture that does not require point-to-point connections from the central controller to every module. The presented approach is verified by time-domain simulations and validated on a downscaled hardware prototype system.

In this paper, the isolation design procedure of a 14.4kV output voltage, 100kHz transformer with an isolation voltage of 115kV using Litz wire is presented. For designing the isolation, a comprehensive design method based on an analytical maximum electrical field evaluation and an electrical field conform design is used. The resulting design is verified by long and short term partial discharge measurements on a prototype transformer.

In this paper, a high precision, low ripple 3kV capacitor charging system is investigated, which is designed for the Compact Linear Collider (CLIC). The 240 kW charging system consists of six capacitor charging units operated in boundary conduction mode (BCM). In order to obtain a low current ripple, the charging currents of the units are interleaved. Measurements of the interleaved capacitor charging are provided, which show the stable operation of the interleaving controller. To achieve a high pulse to pulse repeatability of the pulse modulator system, a high charging accuracy of the capacitor bank is mandatory. Thus, a precision analysis of the capacitor charging system is also performed in this paper. With this analysis, the standard deviation of the capacitor bank's voltage is derived for the entire CLIC load operating range, resulting in σv out

In many pulsed-power applications, there is a trend to modulators based on semiconductor technology. For these modulators, high-voltage and high-current semiconductor switches are required in order to achieve a high pulsed power. Therefore, often, high-power IGBT modules or IGCT devices are used. Since these devices are based on bipolar technology, the switching speed is limited, and the switching losses are higher. In contrast to bipolar devices, unipolar ones (e.g., SiC JFETs) basically offer a better switching performance. Moreover, these devices enable high blocking voltages in the case where wide-band-gap materials, for example, SiC, are used. At the moment, SiC JFET devices with a blocking voltage of 1.2 kV per JFET are available. Alternatively, the operating voltage could be increased by connecting N JFETs and a low-voltage MOSFET in series, resulting in a super cascode switch with a blocking voltage N times higher than the blocking voltage of a single JFET. For the super cascode, auxiliary elements are required for achieving a statically and dynamically balanced voltage distribution in the cascode. In this paper, a new balancing circuit, which results in faster switching transients and higher possible operating pulse currents, is presented and validated by measurement results.

Over the last years, more and more SiC power semiconductor switches have become available in order to prove their superior behavior. A very promising device is the 1200 V 30 A JFET manufactured by SemiSouth. It features a very low on-resistance per die area (2.8 mΩ-cm2), switching within 20 ns, normally off characteristic, high-temperature operation and has already been commercialized in contrast to many other SiC switches. To fully exploit the potential of the SiC normally off JFET, conventional gate drivers for unipolar devices must be adapted to this device due to its special requirements. During on-state, the gate voltage must not exceed 3 V, while a current of around 300 mA (depending on the desired on-resistance) must be fed into the gate; during switching operation, the transient gate-source voltage should be around ±15 V and the low threshold voltage of less than 0.7 V requires a high noise immunity which is a severe challenge as the device has a comparably low gate-source but high gate-drain capacitance. To meet these requirements, several concepts have been published recently. They deal with the challenges mentioned, but they still show certain limitations (e.g., frequency and duty cycle limitations or need for additional cooling due to high gate driver losses). In this paper, a novel gate driver consisting of only one standard gate driver IC, resistors, capacitors, and diodes is designed and experimentally validated. It supplies enough gate current for minimum on-resistance, allows fast switching operation, features a high noise immunity, and can be used for any duty cycle and typical switching frequencies without significant self-heating.

In modern power electronic systems, voltages across inductors or transformers generally show rectangular shapes, including periods of zero voltage. In the stage of zero applied voltage (constant flux), core losses are not necessarily zero. At the beginning of a period of constant flux, losses still occur in the material. This is due to relaxation processes. A physical explanation about magnetic relaxation is given and a new core-loss modeling approach that takes relaxation effects into consideration is introduced. The new loss model is called improved-improved generalized Steinmetz equation and it has been verified experimentally., IEEE Transactions on Power Electronics, 27 (2), ISSN:0885-8993, ISSN:1941-0107

The development of new converter systems with higher power density and/or efficiency offers many degrees of freedom for the design parameters as a large number of system component values have to be defined, where all of which are interdependent, to some extent, on another. Therefore, an automated optimization procedure, based on comprehensive analytical models and the resulting optimal design parameters, e.g., switching frequency or transformer design, to achieve the most compact and/or efficient design, is presented in this paper. In addition, the design of a volume-optimized 400/46-56-V phase-shift dc-dc converter with a current doubler rectifier and the underlying analytical models are also introduced. The power density of the converter is increased by integrating the output inductors in the transformer's core. A new lossless magnetic snubber circuit is introduced, which damps the intrinsic voltage ringing of the rectifier diodes and feeds the ringing energy to the output. The experimental results prove the analytical models and the design procedure. The 5-kW dc-dc converter prototype has a power density of 147 W/in 3 (9 kW/L) and a maximum efficiency of 94.4% at 54-V output voltage and full load., IEEE Transactions on Industrial Electronics, 58 (10), ISSN:0278-0046, ISSN:1557-9948

Switching devices based on wide bandgap materials such as silicon carbide (SiC) offer a significant performance improvement on the switch level (specific on resistance, etc.) compared with Si devices. Well-known examples are SiC diodes employed, for example, in inverter drives with high switching frequencies. In this paper, the impact on the system-level performance, i.e., efficiency, power density, etc., of industrial inverter drives and of dc-dc converter resulting from the new SiC devices is evaluated based on analytical optimization procedures and prototype systems. There, normally on JFETs by SiCED and normally off JFETs by SemiSouth are considered.

For the generation of short high-power pulses in many applications, power modulators based on capacitor discharge are used, where the peak power is drawn from the input capacitor bank. In order to continuously recharge the energy buffer during operation at a lower average power, usually, power supplies connected to the mains are used. Due to the worldwide variation in mains voltages and the desired ability to adapt the capacitor voltage of the modulator, the power supply has to support a wide input and output voltage range, whereby the supply should draw a sinusoidal current from the mains due to EMI regulations. Additionally, depending on the modulator concept, a galvanic isolation also has to be provided. In order to achieve the mentioned specifications for the considered power supply, a combination of an ac-dc and a dc-dc converter is proposed, whereas the mains voltage is rectified by a three-phase buck-boost converter to 400 Vdc, and thereafter, an isolated dc-dc converter charges the input capacitor bank of the power modulator up to 3.5 kV. This paper focuses on the basic operation and the design of the 3.5-kV/11-kW isolated dc-dc converter, which includes transformer design, efficiency-volume optimization, and component selection. In this paper, compared with the well-known flyback converter, the proposed full-bridge-based topology results in a much higher efficiency and power density.

Since SiC VJFETs are believed to offer extremely fast turn on and turn off processes it is important to understand how these transients are tailored by the layout. Regarding the basic layouts two main topologies are under investigation today – structures with the well known SIT layout with purely vertical current flow and lateral vertical concepts where the current flow through the channel is in lateral direction and the vertical current flow takes place in the drift region only. In this paper we will focus on differences in the electric characteristics of both structures and the relation of the dynamic behavior to the topology and the layout of the switches. For the analysis, 1200V VJFETs based on the two basic topologies were manufactured having approximately the same total and active device area. It turns out that the SIT switches under investigation suffer from a high internal gate resistance in the p-doped layers and a relatively high gate drain capacitance.

The demand for decreasing cost and volume and also for increasing efficiency leads to a constantly increasing power density of converter systems. For maximizing the power density of a 5 kW telecom supply, an optimization procedure that automatically balances the switching frequency, semiconductor and passive losses, and thermal performance has been developed. This procedure and the belonging analytical converter and transformer models are presented in this paper. Moreover, the resulting optimized design, which has a power density of 10 kW/dm 3 and an efficiency of 94.5% at a height of 1 U, is presented.

In many applications, a current measurement that can measure AC currents with DC offset is required. This is not possible using conventional current transformers (CTs) due to the core saturation because of the DC offset. In this paper, a new sensor concept is presented, which consists of a wideband CT and a demagnetizing circuit. The sensor concept is capable of measuring AC currents with DC offset, which have periodic zero crossings, as given in power-factor-corrected (PFC) circuits. Using the demagnetization circuit, the core is actively reset during the zero crossing intervals. The operation principle and design equations are discussed in detail in this paper. For validating the presented concept, three sensors have been built using different core materials, and measurements of the transfer functions as well as operation in a PFC system are presented. A bandwidth from DC up to 20 MHz has been achieved.

The design of a single-phase boost power-factor-correction (PFC) circuit is associated with a large variety of considerations, such as the following questions. Which operation mode should be selected (e.g., continuous or discontinuous operation)? How many interleaved boost cells are advantageous? Which switching frequency should be selected? What is the optimum number of EMI input filter stages? Which semiconductor technology should be chosen? All these issues have a significant influence on the converter efficiency and power density. In this paper, the aforementioned questions are addressed for exemplary specifications of the PFC (300-W output power, 400-V output voltage, and 230-V mains voltage), whereby the focus in the design is mainly put on very high power density. As a result, different design points are identified and comparatively evaluated. By considering different aspects such as volume, losses, capacitor lifetime, and also cost issues (e.g., by additional current sensors or expensive silicon carbide devices), a dual-interleaved PFC operated in discontinuous conduction mode at 200 kHz is selected. With an experimental prototype, a superior power density of 5.5 kW/L and a system efficiency of 96.4% are achieved, which is close to the values predicted by the design procedure. Furthermore, measurements verify a near-unity power factor (PF = 99.7%) and the compliance with electromagnetic compatibility conducted noise emission standards. Finally, it is investigated to which extent the power density could be further increased by an integration of the input filter in the PCB.

A three-phase Y-rectifier is formed by the star connection of single-phase unity-power-factor rectifier systems and represents a highly interesting concept for the realization of the input stage of high-power telecommunications power supply modules using established single-phase technology. However, for stable operation, control and balancing of the independent DC output voltages of the phase rectifier systems is required. A novel, easy-to-implement DC output voltage control concept is proposed in this paper. Here, the mean value of all three DC output voltages is controlled, and, in addition, always two out of the three DC voltages are compared and balanced. The basic operating principle of the control is described, the theoretical limit for the admissible asymmetric loading of the DC voltages is calculated, and numeric results for a 10-kW system are given. Finally, the theoretical considerations are verified by measurements on a 3 times1 kW Y-rectifier prototype.

The demand for decreasing costs and volume leads to a constantly increasing power density of industrial converter systems. In order to improve the power density, further different aspects, like thermal management and electromagnetic effects, must be considered in conjunction with the electrical design. Therefore, a comprehensive optimization procedure based on analytical models for minimizing volume of DC-DC converter systems has been developed at the power electronic systems laboratory of the Swiss Federal Institute of Technology (ETH Zurich). Based on this procedure, three converter topologies-a phase-shift converter with current doubler and with capacitive output filter and a series-parallel resonant converter-are optimized with respect to power density for a telecom supply (400 V/48 V). There, the characteristic of the power density, the efficiency, and the volume distribution between the components as functions of frequency are discussed. For the operating points with maximal power density, the loss distribution is also presented. Furthermore, the sensitivity of the optimum with respect to junction temperature, cooling, and core material is investigated. The highest power density is achieved by the series-parallel resonant converter. For a 5-kW supply, a density of approximately 12 kW/L and a switching frequency of ca. 130 kHz are obtained.