1. System-Level Simulation and Fabrication of On-Chip Fatigue Bending Test Structure for Micro-Scale Polysilicon Films
- Author
-
Le Guan, Bin Li, Jia Li Gao, Qi Liu, and Jinkui Chu
- Subjects
Microelectromechanical systems ,Engineering ,Fabrication ,business.industry ,Mechanical Engineering ,Hardware description language ,System-level simulation ,Structural engineering ,Surface micromachining ,Flexural strength ,Mechanics of Materials ,Microelectronics ,General Materials Science ,business ,Actuator ,computer ,computer.programming_language - Abstract
Two kind of on-chip integrated fatigue bending test structures are designed through system-level simulation method based on macromodels to measure the fracture strength and fatigue mechanical properties of polysilicon thin films. The first on-chip fatigue test structure is actuated by V-beam thermal actuator, and the other test structure actuated by electrostatic comb. The static and dynamic analysis was performed by Coventorware Architect module using self-bulid reduced order model described with the MAST hardware language and some other commercial parts from Coventorware parts library. The structural dimension parameters are determined and optimized according to system-level simulation and the computing result has shown that the self-build macromodels and the on-chip integrated test system are efficient and reliable. Two kinds of polysilicon on-chip fatigue bending test structure were fabricated with two-layer polysilicon surface micromachining process in Institute of Microelectronics, Peking University.
- Published
- 2013
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