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Nonlinearities in Radio Frequency Power Transistors can be attributed to mechanisms such as non-linear transconductances and nonlinear capacitances at the device terminals. In this paper, we extend the work in by Ladhani et al to include the impact of the nonlinear gate-source capacitance in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and discuss its contribution (along with the gate baseband impedance) to the amplifier’s intermodulation distortion and linearizability. Measured results show that for a 140W (P1dB (1dB Compression Point)) Class AB LDMOS (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) PA, an optimized gate baseband impedance provides 6dB improvement in corrected ACPR (Adjacent Channel Power Ratio) and 7dB improvement in corrected Alt-1 (First Adjacent Channel Power Ratio) at 7dB backoff from peak power using a 4-Carrier WCDMA (Wideband Code Division Multiple Access) signal.

A compact, pre-matched gallium-nitride (GaN) device is proposed to support high power, high efficiency, concurrent multiband amplifier applications. Novel in-package matching networks addressing both the input and output of high power GaN active devices are considered. As proof-of-concept, a symmetric Doherty power amplifier (PA) with 55.3 dBm (340 W) peak power is demonstrated to achieve 20% fractional RF bandwidth from 1.805 – 2.2 GHz with high efficiency and low baseband impedance. With digital-predistortion (DPD) compensation, the amplifier achieves 48% drain efficiency at average output power of 48.8 dBm, and ACPR better than -52 dBc during concurrent transmission of signals with 395 MHz instantaneous signal bandwidth (ISBW). The results represent the highest linearized efficiency reported for concurrent 3GPP Band 3 and Band 66 multiband scenarios for high power infrastructure PA applications.

The paper extends the concept of waveform shaping for back-off applications which can be applied to realize power amplification sub-blocks in load modulation based power amplifiers. The proposed theory starts with deriving the intrinsic current and voltage waveforms as a function of output power back-off factor. Thereafter, a design methodology is proposed to optimize the performance of power amplifier for back-off requirements within a limit of 3 dB gain compression. For experimental validation, the implementation is carried out using a 1.95 mm gallium nitride (GaN) die. The single-ended PA is designed to operate as a carrier PA in a 35 dBm average asymmetric Doherty configuration (44 dBm peak power). The PA exhibits a drain efficiency of 78% at an average output power of 35 dBm at a frequency of 2.6 GHz.

An integrated passive device (IPD) supporting both RF and baseband impedance matching is proposed that is directly suitable for high power, multiband amplifier applications. The impedance matching method and design techniques are discussed. As proof-of-concept, we present an LDMOS Doherty power amplifier (PA) with 400 W peak power using the proposed IPD to demonstrate 20% fractional RF bandwidth with low baseband impedance. Measurements of the Doherty PA with digital pre-distortion system indicate that the amplifier achieves over 40% drain efficiency at average P out of 48.5 dBm with over 15 dB of gain during concurrent transmission of 3GPP Band 3 & Band 66 from 1.805–2.2 GHz while meeting ACPR of −53 dBc. The results represent over 2 times improvement of instantaneous bandwidth capability over prior work and enables for the first time 395 MHz instantaneous bandwidth capability for high power downlink cellular infrastructure communication systems.

This novel design technique was developed for the input pre-match circuit of discrete base station power amplifiers utilizing multi-section low pass, band pass and high pass topologies by carefully selecting the pole locations to achieve state of the art performance for broadband operation over 20% fractional bandwidth. The techniques have been applied to a 28 V, 230 W LDMOS PA to cover the RF bandwidth from 1.8 GHz to 2.2 GHz with equivalent RF performance for power, gain and efficiency as the narrowband designs while maintaining user-friendly input and load impedances as well as minimal linear phase distortion. To our knowledge, this is the first 28 V LDMOS high power amplifier capable of covering the 20% fractional bandwidth at 2 GHz reported to date.

In this paper we demonstrate high gain, high efficiency, single and balanced Doherty power amplifiers (PAs) that have the ability to transmit signals which occupy the full frequency band from 1930MHz–1995MHz. The PAs have been designed using a new generation of Freescale LDMOS power transistors [1], in which the drain side video-bandwidth (VBW) has been enhanced. For the first time we will show the ability of the PA to handle wideband envelope signals (> 80MHz) with excellent nonlinearity correction using Digital Pre-distortion (DPD). Narrow band as well as wideband DPD measurement results will be presented for single and balanced Doherty PAs including driver stages. These RF Doherty PAs are targeted for use in next generation wideband wireless communication systems.

RF Power Transistors, by design, have an upper limit to the input-signal bandwidth that can be amplified without incurring excessive distortion. The interaction between components internal to the pre-matched RF Power Transistor and on the external circuit board creates resonances at frequencies that are of the order of the modulation bandwidth of the signal. In this paper, we demonstrate a technique to improve the ‘video-bandwidth’ (VBW) capability of RF Power transistors using high-k capacitors. The improvement is more than 2 times a standard device. Also, digital predistortion performance is demonstrated with excellent results for narrow band as well as wideband signals (>50MHz). This capability enables wideband RF Power Amplifier Design for next generation systems demanding wider bandwidth / faster data rates.

This paper presents techniques used in integration for high-power RF semiconductor products and their use in wireless infrastructure power amplifiers. Integrated single and multi-stage devices are discussed, as well as PA architecture comparisons and benefits for class AB, and high efficiency amplifiers. Manufacturing advantages and disadvantages of traditional discrete, versus various types of integrated semiconductor devices are compared for both ground-based and tower-mounted amplifier applications.

A 120 Watt LDMOS radio frequency integrated circuit (RFIC) targeting 1.8 GHz GSM, EDGE, and Evolved EDGE base station applications has been developed using state of the art design techniques and LDMOS technology. The amplifier was designed to cover the 1.8 GHz to 2 GHz GSM bands, and performs exceptionally well under both GSM and EDGE conditions. The two-stage, single-chip design exhibits 27 dB of gain and delivers 132 Watts of output power (1 dB compression; 27 Volt DC supply) with an associated PAE of 51%. Under EDGE modulation, at an average output power of 46 Watts, the EVM is less than 1.6 % and the spectral re-growth is −63 dBc and −78 dBc at 400, and 600 kHz offsets, respectively. This is the highest power, 1.8 to 2 GHz, two-stage RFIC in an over-molded plastic package, reported to date.

This paper presents a dual path 150W Silicon LDMOS 2-stage RF power amplifier designed for WCDMA at 2.2GHz. This device is capable of handling 2 times the UMTS band with flat RF performance. Under a 1 tone CW stimulus, this power amplifier delivers 150W with a power added efficiency of 47% and 29dB linear gain. A 2-stage compact Doherty amplifier constructed of an “in-package” 2 × 75W architecture is also presented, showing the versatility of this unique design. Using the device in a dual-path configuration, this Doherty circuit delivers an increase in drain efficiency of 9–12 points at 8 dB output backoff from P3dB compression, compared to a circuit using the device in a 150W, class-AB reference design.

In this paper we report a method of applying digitally modulated signals to an RF power transistor in a load-pull system. This methodology ensures that the transistor experiences realistic thermal conditions, as well as realistic electrical conditions during test. The measured data is then sliced at constant value of CCDF enabling meaningful performance comparisons to be made between devices and technologies.