Search

This article presents an extensive review of the state-of-the-art system-level solutions featuring complexity reduction and/or dedicated hardware designs for the AV1 and VVC video coding formats. These formats introduced several novel coding techniques compared to their predecessors to improve the coding efficiency at the cost of a significant computational cost. In this article, we discuss the main novelties of AV1 and VVC in each coding module, including block partitioning, intra and inter prediction, transform, entropy coding, and in-loop filters. Then, we present the main published works focusing on complexity reduction and hardware designs for AV1 and VVC. Most of the complexity reduction solutions target the complex and flexible block partitioning structures of these encoders to provide a better tradeoff between coding efficiency and complexity reduction whereas the hardware designs focus on the challenge of implementing the new coding tools to attend real-time processing of high-definition videos. Even with the presented works reaching impressive results, these research fields remain opened for innovative contributions, as discussed in this article.

This article presents the design and hardware implementation of an IGBT-based half-bridge voltage source inverter (VSI) to be used as a basic cell to assemble VSIs of different topologies in modular ways. Herein, we have presented the design methodology and utilized techniques for reducing stray inductances and EMI radiation on the printed circuit board, as well as the way to calculate and select the main electronic components. For the design of the circuit board, local regulations for grid interconnection and international standards were considered in order to obtain a safe and reliable electronic power cell. The developed hardware was subjected to different tests using AC electric motors as loads to validate its design. Two VSIs topologies were evaluated: a single-phase two-level full-bridge inverter and a three-phase two-level inverter. The experimental results validated the theory and demonstrated the excellent performance, reliability, and high efficiency of the developed half-bridge power cell for modular VSIs.

With the recent advances in quantum computing, code-based cryptography is foreseen to be one of the few mathematical solutions to design quantum resistant public-key cryptosystems. The binary polynomial multiplication dominates the computational time of the primitives in such cryptosystems, thus the design of efficient multipliers is crucial to optimize the performance of post-quantum public-key cryptographic solutions. This manuscript presents a flexible template architecture for the hardware implementation of large binary polynomial multipliers. The architecture combines the iterative application of the Karatsuba algorithm, to minimize the number of required partial products, with the Comba algorithm, used to optimize the schedule of their computations. In particular, the proposed multiplier architecture supports operands in the order of dozens of thousands of bits, and it offers a wide range of performance-resources trade-offs that is made independent from the size of the input operands. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt public-key cryptosystem as representative use cases for large-degree binary polynomial multiplications. For each configuration we showed that our template architecture can deliver a performance-optimized multiplier implementation for each FPGA of the Xilinx Artix-7 mid-range family. The experimental validation performed by implementing our multiplier for all the LEDAcrypt configurations on the Artix-7 12 and 200 FPGAs, i.e., the smallest and the largest devices of the Artix-7 family, demonstrated an average performance gain of 3.6x and 33.3x with respect to an optimized software implementation employing the gf2x C library.

Both turbo Hadamard codes and concatenated zigzag Hadamard codes are ultimate-Shannonlimit-approaching channel codes. The former one requires the use of Bahl-Cocke-Jelinek-Raviv (BCJR) in the iterative decoding process, making the decoder structure more complex and limiting its throughput. The latter one, however, does not involve BCJR decoding. Hence its decoder structure can be much simpler and can potentially operate at a much higher throughput. In this paper, we investigate the hardware design of a concatenated zigzag Hadamard encoder/decoder system and implement it onto an FPGA board. We design a decoder capable of decoding multiple codewords at the same time, and the proposed system can operate with a throughput of 1.44 Gbps - an increase of 50% compared with the turbo Hadamard encoder/decoder system. As for the error performance, the encoder/decoder system with a 6-bit quantization achieves a bit error rate of 2 × 10-5 at Eb/N0 = -0.2 dB.

The wideband radar intermediate frequency direct acquisition module is used to acquire, process and transmit data, which is an important part of radar system. Based on the current advanced Virtex-7 FPGA board and high-speed ADC card, this article designs the module from two aspects of hardware design and hardware development, including structure design, data flow design, and FPGA top-level design. Then the article researches on some key technologies involved, including JESD204B protocol configuration, data flow transmission, DDR3 buffer design and clock optimisation. Practice has proved that the design of this article can accomplish the task well in practical engineering.

3D-HEVC is the state-of-the-art standard to compress three-dimensional videos. One of the 3D-HEVC novel tools is the DIS tool, which is used to efficiently compress smooth and homogeneous areas of depth maps by using four different prediction modes. The decision of which DIS mode will be used is done through the SVDC similarity criterion in the DIS original definition. This article proposes the substitution of the complex SVDC criterion for simpler and more hardware friendly criteria as SATD, SSE, and SAD. These alternative criteria were evaluated in terms of encoding efficiency and hardware impacts in comparison with the SVDC. Dedicated DIS hardware were designed using each one of each criterion and these designs were described in VHDL and synthesized for TSMC 40 nm. The best results were found with SAD criteria, with losses of only 0.2% in coding efficiency and with expressive gains of more than 50 times in power and more than 35 times in area, when compared with SVDC. The reached results showed that the use of a simpler similarity criterion is an important alternative to be used in DIS tool, mainly if an efficient hardware design is required.

Hardware in the loop is a widely used technique in power electronics, allowing to test and debug in real time (RT) at a low cost. In this context, field-programmable gate arrays (FPGAs) play an important role due to the high-speed requirements of RT simulations, in which area optimization is also crucial. Both characteristics, area and speed, are affected by the numerical formats (NFs) and their rounding modes. Regarding FPGAs, Xilinx is one of the largest manufacturers in the world, offering Vivado as its main design suite, but it was not until the release of Vivado 2020.2 that support for the IEEE NF libraries of VHDL-2008 was included. This work presents an exhaustive evaluation of the performance of Vivado 2020.2 in terms of area and speed using the native IEEE libraries of VHDL-2008 regarding NF. Results show that even though fixed-point NFs optimize area and speed, if a user prefers the use of floating-point NFs, with this new release, it can be synthesized—which could not be done in previous versions of Vivado. Although support for the native IEEE libraries of VHDL-2008 was included in Vivado 2020.2, it still lacks some issues regarding NF conversion during synthesis while support for simulation is not yet included, This research received no external funding

This work describes an efficient implementation of the iterative decoder that is the main part of the decryption stage in the LEDAcrypt cryptosystem, recently proposed for post-quantum cryptography based on low-density parity-check (LDPC) codes. The implementation we present exploits the structure of the variables in order to accelerate the decoding process while keeping the area bounded. In particular, our focus is on the design of an efficient multiplier, the latter being a fundamental component also in view of considering different values of the cryptosystem’s parameters, as it might be required in future applications. We aim to provide an architecture suitable for low cost implementation on both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations. As for the FPGA, the total execution time is 0.6 ms on the Artix-7 200 platform, employing at most 30% of the total available memory, 15% of the total available Look-up Tables and 3% of the Flip-Flops. The ASIC synthesis has been performed for both STM FDSOI 28 nm and UMC CMOS 65 nm technologies. After logic synthesis with the STM FDSOI 28 nm, the proposed decoder achieves a total latency of 0.15 ms and an area occupation of 0.09 mm2. The post-Place&Route implementation results for the UMC 65 nm show a total execution time of 0.3 ms, with an area occupation of 0.42 mm2 and a power consumption of at most 10.5 mW.

Critical infrastructures and associated real time Informational systems need some security protection mechanisms that will be able to detect and respond to possible attacks. For this reason, Anomaly Detection Systems (ADS), as part of a Security Information and Event Management (SIEM) system, are needed for constantly monitoring and identifying potential threats inside an Information Technology (IT) system. Typically, ADS collect information from various sources within a CI system using security sensors or agents and correlate that information so as to identify anomaly events. Such sensors though in a CI setting (factories, power plants, remote locations) may be placed in open areas and left unattended, thus becoming targets themselves of security attacks. They can be tampering and malicious manipulated so that they provide false data that may lead an ADS or SIEM system to falsely comprehend the CI current security status. In this paper, we describe existing approaches on security monitoring in critical infrastructures and focus on how to collect security sensor&ndash, agent information in a secure and trusted way. We then introduce the concept of hardware assisted security sensor information collection that improves the level of trust (by hardware means) and also increases the responsiveness of the sensor. Thus, we propose a Hardware Security Token (HST) that when connected to a CI host, it acts as a secure anchor for security agent information collection. We describe the HST functionality, its association with a host device, its expected role and its log monitoring mechanism. We also provide information on how security can be established between the host device and the HST. Then, we introduce and describe the necessary host components that need to be established in order to guarantee a high security level and correct HST functionality. We also provide a realization&ndash, implementation of the HST overall concept in a FPGA SoC evaluation board and describe how the HST implementation can be controlled. In addition, in the paper, two case studies where the HST has been used in practice and its functionality have been validated (one case study on a real critical infrastructure test site and another where a critical industrial infrastructure was emulated in our lab) are described. Finally, results taken from these two case studies are presented, showing actual measurements for the in-field HST usage.

Human detection, identification, and monitoring are essential for many applications aiming to make smarter the indoor environments, where most people spend much of their time (like home, office, transportation, or public spaces). The capacitive sensors can meet stringent privacy, power, cost, and unobtrusiveness requirements, they do not rely on wearables or specific human interactions, but they may need significant on-board data processing to increase their performance. We comparatively analyze in terms of overall processing time and energy several data processing implementations of multilayer perceptron neural networks (NNs) on board capacitive sensors. The NN architecture, optimized using augmented experimental data, consists of six 17-bit inputs, two hidden layers with eight neurons each, and one four-bit output. For the software (SW) NN implementation, we use two STMicroelectronics STM32low-power ARM microcontrollers (MCUs): one MCU optimized for power and one for performance. For hardware (HW) implementations, we use four ultralow-power field-programmable gate arrays (FPGAs), with different sizes, dedicated computation blocks, and data communication interfaces (one FPGA from the Lattice iCE40 family and three FPGAs from the Microsemi IGLOO family). Our shortest SW implementation latency is 54.4 μs and the lowest energy per inference is 990 nJ, while the shortest HW implementation latency is 1.99 μs and the lowest energy is 39 nJ (including the data transfer between MCU and FPGA). The FPGAs active power ranges between 6.24 and 34.7 mW, while their static power is between 79 and 277 μW. They compare very favorably with the static power consumption of Xilinx and Altera low-power device families, which is around 40 mW. The experimental results show that NN inferences offloaded to external FPGAs have lower latency and energy than SW ones (even when using HW multipliers), and the FPGAs with dedicated computational blocks (multiply-accumulate) perform best.

The real-time simulation of modular multilevel converter (MMC) is essential to the evaluation and validation of its control and protection systems. Moreover, the dynamics at both sub-module level and system-level are expected from the real-time simulations of MMCs. To achieve this objective, this paper proposes the shifted phasor modeling (SPM) of the MMC by representing each sub-module with a Thevenin equivalent circuit that is derived using shifted phasors with improved accuracy. The efficiency of the SPM is guaranteed by modeling each arm as a switch-dependent Thevenin equivalent circuit. The computational burden remains almost unchanged even when the number of sub-modules increases considerably. The proposed model is materialized using eld programmable gate array. And, thus the real-time simulation of MMC-based DC grids can be realized to capture the dynamics at the system level as well as the submodule level. The effectiveness of this paper has been validated in terms of both accuracy and efficiency on a two-terminal MMC-based low-voltage direct current system.

WOS:000448616200009; The major challenge to Exaflop computing, and more generally, efficient high-end computing, is in finding the best "matches" between advanced hardware capabilities and the software used to program applications, so that top performance will be achieved. Several benchmarks show very disappointing performance progress over the last decade, clearly indicating a mismatch between hardware and software. To remedy this problem, it is important that key performance enablers at the software level-autotuning, performance analysis tools, full application optimization-are understood. For each area, we highlight major limitations and most promising approaches to reaching better performance and energy levels. Finally, we conclude by analyzing hardware and software design, trying to pave the way for more tightly integrated hardware and software codesign.

[EN] This work presents a set of laboratory experiments that can be carried out by students who are taking digital design courses in engineering programs like Electronics, Communications Systems and Mechatronics. The purpose of these labs is to help students develop their skills and confidence designing arithmetic hardware blocks through solving of specific problems. In this aspect, this paper shows a method to be followed in the laboratory to design arithmetic blocks and implement them in microcontrollers and FPGAs. More specifically, the block design of a number's multiplicative inverse (1/root x), its square root (root x) and the square root of its inverse (1/root x) are presented. To complete these exercises, knowledges on Newton-Raphson algorithm, difference equations and digital design are required. Students of our institution completed the lab practices, and after analyzing the results from student surveys and classroom observations, we found out that completing these tasks significantly contributed to the students' training in the hardware design field., Este trabajo fue financiado por el Consejo Nacional de Ciencia y Tecnología (CONACYT) de México, mediante el proyecto de Ciencia Básica número 241272

This paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us.

The Advanced Microcontroller Bus Architecture Advanced eXtensible Interface is a memory mapped protocol intended for internal System on Chip communications. However, there is no mean to directly exchange data between AXI devices and LabVIEW applications. This work proposes a novel and streamlined bridge solution to transfer data directly and effectively from/to an AXI target memory and any LabVIEW FPGA application, essential to integrate AXI-based architectures into PXI FPGA peripheral modules. The block diagram of the proposed IP solution and synthesis results are presented for target programmable devices of interest.

Considering code-based cryptography, quasi-cyclic low-density parity-check (QC-LDPC) codes are foreseen as one of the few solutions to design post-quantum cryptosystems. The bit-flipping algorithm is at the core of the decoding procedure of such codes when used to design cryptosystems. An effective design must account for the computational complexity of the decoding and the code size required to ensure the security margin against attacks led by quantum computers. To this end, it is of paramount importance to deliver efficient and flexible hardware implementations to support quantum-resistant public-key cryptosystems, since available software solutions cannot cope with the required performance. This manuscript proposes an efficient and scalable architecture for the implementation of the bit-flipping procedure targeting large QC-LDPC codes for post-quantum cryptography. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt cryptosystem as representative use cases for QC-LDPC codes suitable for post-quantum cryptography. For each configuration, our template architecture can deliver a performance-optimized decoder implementation for all the FPGAs of the Xilinx Artix-7 mid-range family. The experimental results demonstrate that our optimized architecture allows the implementation of large QC-LDPC codes even on the smallest FPGA of the Xilinx Artix-7 family. Considering the implementation of our decoder on the Xilinx Artix-7 200 FPGA, the experimental results show an average performance speedup of 5 times across all the LEDAcrypt configurations, compared to the official optimized software implementation of the decoder that employs the Intel AVX2 extension.

International audience; Applying rotated and cyclic Q delayed (RCQD) modulation on the transmitter side improves the performance of the receiver in case of fading channel conditions along with erasures. However, the complexity of demapping in the receiver increases significantly to achieve this elevated performance. Many low complexity demapping solutions are available but few are actually implemented in hardware. Recently, new constellation rotation angles and associated simplified demapping technique with better performance for fading channel conditions along with erasure scenarios has been proposed. In this paper, we propose a novel demapper architecture model that exploits these latest simplifications. Moreover, a joint demapper implementation is proposed, which can demap the symbols from different constellations using full or simplified demapping algorithm to achieve best throughput in terms of LLR/sec. Compared to state-of-the-art implementations of RCQD demappers, significant hardware reductions are demonstrated encouraging the use of RCQD modulation in future wireless communication applications.

International audience; Asynchronous circuits have key advantages in terms of low energy consumption, robustness, and security. However , the absence of a global clock makes the design prone to deadlock, livelock, synchronization, and resource-sharing errors. Formal verification is thus essential for designing such circuits, but it is not widespread enough, as many hardware designers are not familiar with it and few verification tools can cope with asyn-chrony on complex designs. This paper suggests how an industrial design flow for asynchronous circuits, based upon the standard HDL SystemVerilog, can be supplemented with formal verification capabilities rooted in concurrency theory and model-checking technology. We demonstrate the practicality of our approach on an industrial asynchronous circuit (4000 lines of SystemVerilog) implementing a memory protection unit.

This paper presents a general-purpose data collection system that combines a DSLR camera with directional LED lamps in order to capture a large quantity of high-resolution manuscript images in such a way as to maximize the speed of data collection while minimizing time and the need for specialized equipment. By integrating custom image processing software, the captured document images are mapped to lie on a planar surface, thereby enabling the application of more sophisticated computer vision algorithms. For this purpose, we also introduce an optional binarization tool that allows researchers to perform basic image pre-processing to simplify later analysis. The hardware setup and software tools presented in this paper can be combined to yield a simple system capable of producing large image datasets for use in document analysis research projects. Scopus

This paper proposes a series of proactive hybrid high-voltage direct-current (HVDC) breaker (HHB) electromagnetic transient models that can be implemented in hardware-in-the-loop (HIL) emulation for real-time execution on the field-programmable gate array (FPGA). To achieve high fidelity, an HHB model should have the same configuration as the real one, and three different models for an insulated-gate bipolar transistor (IGBT), i.e., a two-state switch model, a curve-fitting model, and an improved nonlinear behavioral model, are proposed to satisfy different accuracy and simulation speed requirements. Since designing an HHB with hundreds of IGBTs in a massive array would lead to an extremely heavy computational burden as well as to a high FPGA resource utilization, circuit partitioning is applied to each model, which enables decomposition into a number of physically independent subcircuits with smaller matrix dimension to exploit parallel implementation. Meanwhile, low hardware resource demand is achieved by using one of the subcircuits to represent the rest since they are identical. As the IGBTs produce a significant amount of heat, which in turn affects their performance, an electrothermal network is added as part of the model to provide specific information about the device’s operation status including the junction temperature. The models are applied to a three-terminal HVDC system, where line faults are simulated to activate HHB protection sequence. Comparison of device-level and system-level performance from HIL emulation with those of commercial offline simulation tools validates the accuracy of the proposed models as well as the efficacy of the solution approach.

The Smart Transformer (ST) has been proposed for increasing the hosting capacity of renewable energy sources in the power system with advanced control and communication capability. Its capability to connect-and disconnect itself from the main grid and to provide power from the Low Voltage (LV) grid to the Medium Voltage (MV) grid in the grid forming mode are an opportunity to realize an islanded operation mode. This operation mode requires a suitable controller design, which is forming the MV grid and the LV grid at the same time. This work proposes a modular ST architecture consisting of a three phase Cascaded H-Bridge (CHB) converter connected to Quadruple Active Bridge (QAB) converters. The design of the converter and its magnetic components is examined as well as the controller design for the QAB for the capability to address different operation modes. Grid forming operation on the both AC grid sides and the resulting constraints by means of active power availability are examined as well as opportunities to influence the power consumption of the grids. An experimental setup is presented and selected operation modes are demonstrated.

International audience; Several technical contributions are emerging nowadays to fulfill the new requirements foreseen in the 5th generation (5G) of mobile communication systems. Among these contributions, different variants of waveform design are proposed for the new radio air interface as alternative to orthogonal frequency-division multiplexing (OFDM) adopted in 4G. However, in order to prove the feasibility and the benefits of the proposed waveforms, practical hardware implementations are necessary. This paper presents one of the first flexible and efficient hardware platform for waveform design proof-of-concept. The proposed platform constitutes a complete hardware/software development environment, with digital processing, radio frequency boards, and all associated interfaces for control, communication, and display. Promising waveform candidates are implemented, in addition to OFDM, with careful architectural choices to allow fair comparisons. Furthermore, the proposed platform allows the support of several communication scenarios as foreseen in 5G.

For highly demanding scenarios such as continuous bio-signal monitoring, transmitting excessive volumes of data wirelessly comprises one of the most critical challenges. This is due to the resource limitations posed by typical hardware and communication technologies. Driven by such shortcomings, this paper aims at addressing the respective deficiencies. The main axes of this work include (a) data compression, and (b) the presentation of a complete, efficient and practical hardware accelerator design able to be integrated in any Internet of Things (IoT) platform for addressing critical challenges of data compression. On one hand, the developed algorithm is presented and evaluated on software, exhibiting significant benefits compared to respective competition. On the other hand, the algorithm is fully implemented on hardware providing a further proof of concept regarding the implementation feasibility with respect to state-of-the art hardware design approaches. Finally, system-level performance benefits, regarding data transmission delay and energy saving, are highlighted, taking into consideration the characteristics of prominent IoT platforms. Concluding, this paper presents a holistic approach based on data compression that is able to drastically enhance an IoT platform’s performance and tackle efficiently a notorious challenge of highly demanding IoT applications such as real-time bio-signal monitoring

The neuroregulator system in humans controls organ and system functioning. This system comprises a set of neural centres that are distributed along the spinal cord and act independently together with their nerve interconnections. The centres involved in this task were isolated in previous studies through investigations of the functioning and composition of the neuroregulator system of the lower urinary tract to elucidate their individual performances and enable the creation of a general neuroregulator system model capable of operating at the neuronal level. Although the long-term goal of our research is the development of a system on chip (SoC) capable of behaving as a fully programmable neuroregulator system, this work is another step in which we test the viability of the hardware design of one of these neuroregulator centres (specifically the cortical-diencephalic centre) to achieve a first prototype and architectural proposal. To this end, the behaviour of this centre has been isolated, a hardware design implemented on FPGA has been proposed to create a prototype, a simulation environment has been built for the evaluation, and finally, the results have been analysed. This system verified that the functional behaviour corresponded to the expected behaviour in humans and that the operational requirements for the implementation were technically and architecturally viable. We propose a hardware design of the Cortical-Diencephalic centre.We have implemented the hardware design on FPGA system.We analysed the results and verified that the functional behaviour corresponded to the expected behaviour in humans.

Integration of hardware accelerators in System on Chips is often complex. When dealing with reconfigurable hardware, this greatly limits the attainable flexibility. In this paper, we propose an approach based on a dedicated instruction set designed to manage data transfer and execution. This approach, named Ouessant, is based on a very simple general purpose instruction set designed for close interaction with dedicated hardware accelerators. This instruction set is used to program a dedicated controler, which commands the accelerator's execution and data transfer with minimal CPU intervention. The resulting architecture is flexible, extensible, and can be easily integrated in System on Chips. Adding new accelerators is also made easier. Implementation of the architecture on different FPGA resources show very low footprint and a very small impact on attainable performance. Ouessant is freely available under an open-source license.

in the present mobile data transmission methods, only WLAN has the high data rate supporting video service, so it will necessarily be an important part of future personal communication networks. This paper researches into the characteristics and technologies of WLAN, analyses the properties and features of stochastic competitive MAC protocol, and designs a high-rate WLAN terminal card, which is based on IEEE802.11 protocol. The card applies Direct-Sequence Spread-Spectrum technology, can support a highest data rate at 11Mbps and meet the high-rate wireless access requirement.

This paper presents an image processing application focused on robotic computer vision. The co- design is divided into three main parts: a hardware accelerator, a PCIe® based framework for HW/SW link, and application software. The implemented accelerator performs preprocessing for facial recognition in order to reduce the workload in the main system processor. The hardware layer is implemented in Altera FPGAs, while the project software layer provides a device driver for Linux to link the user application with the coprocessor. The user application controls the data transfer between the operating system and the device driver. The platform allows rapid prototyping of accelerators, taking advantage of the duality of a programmable hardware and a general purpose processor connected through a PCIe® link. The proposed architecture enables co- design of various image processing algorithms. In this case, the results of the design of an accelerator that performs histogram equalization for contrast correction of color images are presented.

The amount of resources available on reconfigurable logic devices like FPGAs has seen a tremendous growth over the last thirty years. During this period, the amount of programmable resources (CLBs and RAMs) has increased by more than three orders of magnitude. Programming these reconfigurable architectures has been dominated by the hardware description languages VHDL and Verilog. However, it has become generally accepted that these languages do not provide adequate abstraction mechanisms to deliver the design productivity for designing more and more complex applications. To raise the abstraction level, techniques to translate high-level languages to hardware have been developed based on imperative languages like C. Parallelism is achieved by parallelization of for-loops. Whether parallelization of loops is possible, is determined using dependency analysis which is a very hard problem. To mitigate this problem, other abstractions are needed to express parallelism. In this thesis, parallelism is expressed using higher-order functions, an abstraction commonly used in functional programming languages. The main contribution of this thesis is a design methodology based on exploiting regularity of higher-order functions. A mathematical formula, e.g., a DSP algorithm, is first formulated using higher-order functions. Then, transformation rules are applied to these higher-order functions to distribute computations over space and time. Using these transformations, an optimal trade-off can be made between space and time. Finally, hardware is generated using the CLaSH compiler by translating the result of the transformation to VHDL. In this thesis, we derive transformation rules for several higher-order functions and prove that the transformations are meaning-preserving. After transformation, a mathematically equivalent description is derived in which the computations are distributed over space and time. The designer can control the amount of parallelism using a parameter that is introduced by the transformation. Transformation rules for both one-dimensional higher-order functions and two-dimensional higher- order functions have been derived and applied to several case studies: a dot product, a particle filter and stencil computations.

International audience; PNG (Portable Network Graphics) is a lossless compression method for real-world pictures. Since its specification, it continues to attract the interest of the image processing community. Indeed, PNG is an extensible file format for portable and well-compressed storage of raster images. In addition, it supports all of Black and White (binary mask), grayscale, indexed-color, and truecolor images. Within the framework of the Demat+ project which intend to propose a complete solution for storage and retrieval of scanned documents, we address in this paper a hardware design to accelerate the PNG encoder for binary mask compression on FPGA. For this, an optimized architecture is proposed as part of an hybrid software and hardware cooperating system. For its evaluation, the new designed PNG IP has been implemented on the ALTERA " Arria II GX EP2AGX125EF35 " FPGA. The experimental results show a good match between the achieved compression ratio, the computational cost and the used hardware resources.

Compressive sensing (CS) is a signal acquisition strategy that, based on the assumption of sparsity, promises to relax the design constraints of signal acquisition systems with respect to conventional strategies. In this paper, we contrast signal acquisition systems for low-rate applications based on analog CS encoding with systems based on digital CS encoding. We consider the complete signal chain from acquisition to reconstruction, with particular attention to the effects of quantization, and show that the two schemes differ significantly in encoder precision, measurement resolution, compression ratio, and reconstruction quality. Further, we develop first-order power estimation models to asses the relative energy-efficiency of different CS and conventional signal acquisition systems. Our numerical evaluations suggest that when the power consumption of data storage/communication outweighs the power consumption of data acquisition and processing, analog CS systems can outperform their digital counterparts, despite their higher hardware complexity. Moreover, we provide evidence that the common special case of analog and digital encoding, known as non-uniform sampler, performs best under all conditions.

Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in modern Information Systems (IS). Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show how these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound conservative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.

International audience; Abstract—This paper presents a hardware implementation of asoft-decision Reed-Solomon (RS) decoder, based on the stochasticChase algorithm. This decoder achieves a coding gain of at least0.45 dB at FER=10−4 for the well-known RS(255,239) code. Tothe best of our knowledge this is the highest reported codinggain for a hardware implementation of soft-decision RS(255,239)decoder. The decoder is implemented on a Virtex-5 FPGAand works at 800 Mb/s. The proposed decoder has a flexiblearchitecture and is well suited for applications requiring differentthroughputs and decoding performance.

Due to the increasing design size and complexity of modern Integrated Circuits (IC) and the decreasing time-to-market, debugging is one of the major bottlenecks in the IC development cycle. This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging. The approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. The experimental results show the effectiveness of the approach in post-silicon debugging.

We present FAuST, an extensible framework for Formal verification, Automated debugging, and Software Test generation. Our framework uses a highly customizeable Bounded Model Checking (BMC) algorithm for formal reasoning about software programs and provides different applications, e.g., property checking, functional equivalence checking, test case generation, and fault localization. FAuST supports dynamic execution and parallel symbolic reasoning using the LLVM compiler infrastructure and an abstraction layer for decision procedures.

Developing usable and robust mixed reality systems requires unique human-computer interaction techniques and customized hardware systems. The design of the hardware is directed by the requirements of the rich 3D interactions that can be performed using immersive mobile MR systems. Geometry modeling and capture, navigational annotations, visualizations, and training simulations are all enhanced using augmented computer graphics. We present the design guidelines that have led us through 10 years of evolving mobile outdoor MR hardware systems.

A methodology for the design of modular and optimized architectural blocks for the generation of local windows of pixels is presented. The proposed formalization and the related techniques follow a design approach derived from the window-based algorithmic decomposition of low- and medium-level image processing algorithms. >

OpenMAC is presented in this study as an innovative reconfigurable platform which overcomes the limitations of state-of-the-art experimental tools to test medium access control (MAC) protocols. The purpose of the OpenMAC platform is to simplify the prototyping process by enabling the implementation of MAC protocols designed in C++, relieving the protocol designer from the hardware and timing aspects, and thus avoiding the need to code optimised C/assembly or hardware description language (HDL). Aiming to reduce the hardware design and implementation costs with respect to custom hardware solutions, the OpenMAC platform has been implemented on an inexpensive off-the-shelf reconfigurable field programmable gate array (FPGA)-based development board with a processor embedded in the FPGA. The challenge presented by the proposed platform is to fulfil strict MAC time-constraints with compiled straightforward and clean C++ code. For this purpose, the OpenMAC platform introduces an innovative hardware/software partitioning concept for MAC protocol implementation which is based on a shared-memory architecture. Measurements carried out on an FPGA board demonstrate that this platform meets the short inter-frame space (SIFS) specification of the IEEE 802.11 standard, hence enabling field testing of prototyped MAC protocols.

International audience; Hardware process calculi, such as CHP (Communicating Hardware Processes), Balsa, or Haste (formerly Tangram), are a natural approach for the description of asynchronous hardware architectures. These calculi are extensions of standard process calculi with particular synchronisation features implemented using handshake protocols. In this article, we first give a structural operational semantics for value-passing CHP. Compared to the existing semantics of CHP defined by translation into Petri nets, our semantics is general enough to handle value-passing CHP with communication channels open to the environment, and is also independent of any particular (2- or 4-phase) handshake protocol used for circuit implementation. We then describe the translation of CHP into the process calculus LOTOS (ISO standard 8807), in order to allow asynchronous hardware architectures expressed in CHP to be verified using the CADP verification toolbox for LOTOS. A translator from CHP to LOTOS has been implemented and successfully used for the compositional verification of two industrial case studies, namely an asynchronous implementation of the DES (Data Encryption Standard) and an asynchronous interconnect of a NoC (Network on Chip).

Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, subportions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually optimized solutions, and orders of magnitude higher than those generated by commercial high-level synthesis tools.

The Information Centric Networking (ICN) paradigm is attracting more and more interest from the research community due to its peculiarities that make it one of the best candidates for constructing the Future Internet. For this reason, there are many papers in literature that study how to transform ICN principles in reality in order to magnify its relevance for the society. In order to provide a solid summary of the state of the art, the present contribution tries to summarize the main findings related to this research field. In particular, an overview on the most important ICN architectures, their main aspects, common networking approaches, and differences, is provided. Moreover, the work carried out in standardization bodies, with particular attention to the list of baseline scenarios defined in this context, is illustrated. Also the main international projects that are trying to integrate ICN networking primitives in pioneering use cases are presented, describing proposed architectures and related challenges for enabling information-centric primitives in current network infrastructures. Finally, the work highlights design principles and core components to build ICN-enabled network devices.

The hardware of networked embedded sensor nodes is in continuous evolution, from those 8-bit MCUs-based platforms such as Mica, up to powerful Edge nodes that even include custom hardware devices, such as FPGAs in the Cookies platform. This evolution process comes up with issues related to the deployment of the Internet of Things, particularly in terms of performance and communication bottlenecks. Moreover, the associated integration process from the Edge up to the Cloud layer opens new security concerns that are key to assure the end-to-end trustability and interoperability. This work tackles these questions by proposing a novel embedded Edge platform based on an EFR32 SoC from Silicon Labs with Contiki-NG OS that includes an ARM Cortex M4 MCU and an IEEE 802.15.4 transceiver, used for resource-constrained low-power communication capabilities. This IoT Edge node integrates security by hardware, adding support for confidentiality, integrity and availability, making this Edge node ultra-secure for most of the common attacks in wireless sensor networks. Part of this security relies on an energy-efficient hardware accelerator that handles identity authentication, session key creation and management. Furthermore, the modular hardware platform aims at providing reliability and robustness in low-power distributed sensing application contexts on what is called the Extreme Edge, and for that purpose a lightweight multi-hop routing strategy for supporting dynamic discovery and interaction among participant devices is fully presented. This embedded algorithm has served as the baseline end-to-end communication capability to validate the IoT hardware platform through intensive experimental tests in a real deployment scenario.