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In this paper, a low power and high performance three-dimensional (3-D) stacking multimedia platform called "3D-PAC" is proposed. This platform is a heterogeneous integration composed of a low power design logic layer (2D-PAC) and a reconfigurable memory tier via 3-D technology. After extensive 3-D architecture exploration with Electronic System Level (ESL) simulation, there is a 54% performance speedup compared with the former 2-D architecture for certain multimedia applications. This chip is fabricated in TSMC 90nm generic CMOS technology. The area of 2D-PAC is about 7880 x 7880 μm2 and the SRAM layer is about 3880 x 3880 μm2. Both layers are combined with 1,886 TSVs.

Today's electronic devices are expected to be fully function, low power consumption and high performance. There are more and more functional modules integrated in a SoC chip. A three-dimension integrated circuit (3-D IC) is developed and in which two or more layers of active electronic components are integrated both vertically into a single circuit. In two-dimension IC, the memory size usually dominated and occupied the most of area. Besides, 3-D IC designs will deal with serious challenges in design space exploration and system validation. In this work, we analyze different system architectures, mainly the architecture of the stacking memory. To demonstrate our 3-D IC design techniques, the stacking memory approach is employed in our “3D-PAC (Parallel Architecture Core)” design. In 3D-PAC, we stack 512KB SRAM directly on top of the logic die which is heterogeneous multi-core computing platform for multimedia application purpose. Finally, we use ESL technology to demonstrate the performance improvement. The result shows that there is 34.89% of speed-up by using the stacking memory architecture.

Traditional technology scaling of semiconductor chips followed Moore's Law. However, the transistor performance improvement will be limited, and designers will not see doubling of operating frequency every two years. Recently, 3-D integrated circuits that utilize through silicon via (TSV) for interconnection have been developed as an improved alternative to the Package-on-Package (PoP) and System-in-Package (SiP) packages. There are many benefits by using TSV-based 3-D integration technologies: (1) Circuit delay can be improved due to the shorter interconnect and reduced parasitic capacitance/inductance, (2) more functionality can be integrated into a small silicon space for form factor reduction and higher packing density due to the additional third dimension, (3) different components with incompatible manufacturing process (i.e. Logic, DRAM, Flash, etc) can be combined in a single 3-D IC for heterogeneous integration. The 3-D integration based on TSV technology enables stacking of multiple memory layers to obtain higher bandwidth for the recent multimedia applications at lower energy consumption. Intel has demonstrated through the teraflops microprocessor chip which is an 80-core design with memory-on-logic architecture. And, each core connects to a 256KB SRAM with 12GB/s bandwidth. Although 3-D IC overcomes many limitations and drawbacks on 2-D IC design, it still has many challenges and design issues that should be considered carefully. In general, the number of TSV is the most critical constraint while designing a 3-D architecture because it is highly related to system performance.

In this paper, we introduce the VLIW DSP subsystem for multi-core software development and SoC prototyping. The DSP subsystem consists two DSP cores (65nm PACDSP V3F) and a FPGA chipset (Virtex5 XC5VLX330), which is a multi-core solution. The flexibility of FPGA makes it easier to integrate two DSP cores into different platforms, and system integrators can accord to their requirement to use different off-chip memory subsystem by implement different memory controller. For high-performance DSP core, thermal issues and power consumption are becoming major design constraints. Temperature variations are adversely affecting the chip reliability. In order to reduce both thermal effects and power dissipations, we develop twelve thermal sensors and several low power design techniques in the DSP subsystem, such as dynamic power management system and thermal-aware configurable instruction memory subsystem. In the DSP subsystem, an energy-effective cell-based design has been produced by analyzing the relationships between the energy efficiency and the synthesis constraints. The DSP core is fabricated in the TSMC 65nm CMOS technology. The estimated power dissipations can save about 12%∼18% by using thermal-aware configurable instruction memory subsystem in H.264 decoder, JPEG decoder and AAC decoder.

Power consumption has been becoming one of the most important criteria for portable embedded devices. During application program development phase to estimate the power consumption is of great significance. In this paper, we propose a power evaluation methodology for PACDSP instruction set simulator. Programmers can easily observe the power consumption during the application development stage. The power modeling is compared with Synopsys PrimeTime PX, and the maximum deviation is less than 4% by executing the BDTI benchmarks. Furthermore, we also discuss the power consumption of the PAC Duo multimedia platform.

Today's embedded systems mostly target on portable devices, which are expected not only to be small, lightweight, fully functional, and real-time, but also to provide extremely long battery lifetime. Therefore, energy-efficiency has become a new challenge. Due to this reason, the power consumption is more and more important for the system on chip (SoC) design. In this paper, we discuss the 65nm DSP subsystem which provides a power optimized DSP subsystem for dual-core software development and SoC prototyping. The most important component of 65nm DSP subsystem is the 65nm Media Platform IC. In the 65nm Media Platform IC, the dynamic voltage & frequency scaling (DVFS) and power gating mechanism have been applied to reduce power dissipations with a novel Unified Power Format (UPF) flow. The 65nm Media Platform IC is fabricated in the TSMC 65nm CMOS technology, of which the estimated power dissipations are 40.97mW for 240MHz @1.0V and 56.47mW for 342MHz @1.2V respectively.