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This paper presents a switched capacitor low-pass filter in a 28-nm fully depleted silicon on insulator CMOS technology for 77-GHz automotive radar applications. It is operated at a power supply as low as 1 V and guarantees 5-dB in-band voltage gain while providing out-of-band attenuation higher than 36 dB and a programmable passband up to 30 MHz. A double sampling technique is adopted, which allows high operating frequency to be achieved while saving power. Moreover, low-voltage biasing and common-mode feedback circuits are exploited to guarantee an almost rail-to-rail output voltage swing. The proposed filter provides an output 1-dB compression point as high as 8.7 dBm with a power consumption of 9 mW. To the authors’ knowledge, this is the first SC-based implementation of a low pass filter for automotive radar applications.

Actually, agricultural surfaces are estimated by the Italian National Statistical Institute (ISTAT) through experts evaluations. The present work has two purposes: 1) to improve the use of administrative data for increasing reliability of crop statistics; 2) to improve methodology for releasing crop early estimates. IACS administrative data are available within a short time lag, cover all the main crops and may substitute estimates gradually. As regards early estimates, the usual design based estimation strategy may be improved through double sampling and model based regression. Results show good reliability of administrative data and decrease of estimates variances using model based estimation. JEL Codes: Q10, Q11, C13, C83.

Microbiological testing represents a significant expenditure for producers. Two new double sampling plans employing a compressed limit in the first stage of inspection were proposed to reduce the testing costs. These plans were designed for sanitary characteristics where the bacterial count generally fits a Poisson or a mixed-Poisson distribution. Both plans showed improved consumer protection with substantially smaller average sample size. The application of the new plans was validated using an empirical dataset of aerobic plate counts observed in milk powder samples. The new plans enabled a sample size reduction of between 20 and 75% compared to the actual sampling procedures.

A new method for on-chip random telegraph noise (RTN) characteristic time constant extraction using the double sampling circuit in an 8.3 Mpixel CMOS image sensor is described. The dependence of the measured RTN on the time difference between the double sampling and the key equation used for time constant extraction are derived from the continuous time RTN model and the discrete event RTN model. Both approaches lead to the same result and describe the data reasonably well. From the detailed study of the noisiest 1000 pixels, we find that about 75% to 85% of them show the signature of a single-trap RTN behavior with three distinct signal levels, and about 96% of the characteristic time constants fall between 1 ${\mathrm{ \mu }}\text{s}$ and 500 ${\mathrm{ \mu }}\text{s}$ with the median around 10 ${\mathrm{ \mu }}\text{s}$ at room temperature.

A disease prevalence can be estimated by classifying subjects according to whether they have the disease. When gold-standard tests are too expensive to be applied to all subjects, partially validated data can be obtained by double-sampling in which all individuals are classified by a fallible classifier, and some of individuals are validated by the gold-standard classifier. However, it could happen in practice that such infallible classifier does not available. In this article, we consider two models in which both classifiers are fallible and propose four asymptotic test procedures for comparing disease prevalence in two groups. Corresponding sample size formulae and validated ratio given the total sample sizes are also derived and evaluated. Simulation results show that (i) Score test performs well and the corresponding sample size formula is also accurate in terms of the empirical power and size in two models; (ii) the Wald test based on the variance estimator with parameters estimated under the null hypothesis outperforms the others even under small sample sizes in Model II, and the sample size estimated by this test is also accurate; (iii) the estimated validated ratios based on all tests are accurate. The malarial data are used to illustrate the proposed methodologies.

This paper introduces a procedure for designing Double Sampling Plan DSP (0, 1) under Bayesian methodology. The optimum plan parameter can be found with Operating Characteristic (OC) curve passes through two-point on the OC curve for respective plan through protection in favor of producer and consumer with specified risks. When prior information about production process is available, then Bayesian methodology is an appropriate procedure to construct the design of parameters. This paper elucidates about the methodology for designing Bayesian Double Sampling Plan using minimum angle method for quality improvement and optimized plan based on the minimum angle method towards minimizing both risks.

A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm2, and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

Purpose: Compare the pain of the kocher incision and midline incision in postoperative patients with cholecystectomy laparotomy. Methods: Observational randomized controlled double sampling trial study Results: Pain that was felt by patients after 24 hours postoperatively with the kocher incision technique, most showed a score of 3, which was 12 patients (60%), whereas pain felt by patients with a midline incision technique mostly showed a score of 2 ie there were 10 patients (50 %). Overall, the midline incision showed lower VAS results when compared to the kocher incision, where most of the VAS in the midline incision showed a score of 2, whereas the kocher incision showed a score of 3. The results of the mann whitney statistical test showed a value of p = 0.192 (p> 0 , 05), which means that there is no significant difference between the pain level of the kocher group and the midline group. Conclusions: There was no significant difference between the level of pain in the group of patients who received the treatment with the kocher technique and the group with the midline technique.

International audience; The double sampling paradigm is an efficient method to protect the circuits against soft-errors. But the data that are going out of the area protected by double sampling are still vulnerable. In this paper we proposed an architectural solution that uses three latches to remove those constraints and protect the area outside the double sampling domain without adding a buffer stage.

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.

Most studies that follow subjects over time are challenged by having some subjects who dropout. Double-sampling is a design that selects, and devotes resources to intensively pursue and find a subset of these dropouts; then uses data obtained from these to adjust naive estimates, which are potentially biased by the dropout. Existing methods to estimate survival from double-sampling assume a random sample. In limited-resource settings however, generating accurate estimates using a minimum of resources is important. We propose using double-sampling designs that oversample certain profiles of dropouts as more efficient alternatives to random designs. First, we develop a framework to estimate the survival function under these profile double-sampling designs. We then derive the precision of these designs as a function of the rule for selecting different profiles, in order to identify more efficient designs. We illustrate using data from a United States President’s Emergency Plan for AIDS Relief (PEPFAR)-funded HIV care and treatment program in western Kenya. Our results show why and how more efficient designs should oversample patients with shorter dropout times. Further, our work suggests generalizable practice for more efficient double-sampling designs, which can help maximize efficiency in resource-limited settings.

This study aims to look into the relationship between the parents`s family history of diabetes and factors of metabolic syndrome focusing on Korean adult males with a family history of diabetes. The data used for the study was collected from the 2010 Korea National Health and Nutrition Examination Survey. The subjects of the study totaled 2,045. For statistical analysis, double sampling general linear regression was used and the statistical significance was p

Double-sampling schemes using one classifier assessing the whole sample and another classifier assessing a subset of the sample have been introduced for reducing classification errors when an infallible or gold standard classifier is unavailable or impractical. Inference procedures have previously been proposed for situations where an infallible classifier is available for validating a subset of the sample that has already been classified by a fallible classifier. Here, we consider the case where both classifiers are fallible, proposing and evaluating several confidence interval procedures for a proportion under two models, distinguished by the assumption regarding ascertainment of two classifiers. Simulation results suggest that the modified Wald-based confidence interval, Score-based confidence interval, two Bayesian credible intervals, and the percentile Bootstrap confidence interval performed reasonably well even for small binomial proportions and small validated sample under the model with the conditional independent assumption, and the confidence interval derived from the Wald test with nuisance parameters appropriately evaluated, likelihood ratio-based confidence interval, Score-based confidence interval, and the percentile Bootstrap confidence interval performed satisfactory in terms of coverage under the model without the conditional independent assumption. Moreover, confidence intervals based on log- and logit-transformations also performed well when the binomial proportion and the ratio of the validated sample are not very small under two models. Two examples were used to illustrate the procedures.

International audience; Aggressive technology scaling has dramatic impact on process, voltage and temperature (PVT) variations; circuit aging and wearout; clock skews; sensitivity to EMI (e.g. crosstalk and ground bounce), sensitivity to radiation-induced SEUs SETs; as well as power dissipation and thermal constraints. The resulting high defect rates and design complexity, adversely affect fabrication yield and reliability.

Since the run length distribution is generally highly skewed, a significant concern about focusing too much on the average run length (ARL) criterion is that we may miss some crucial information about a control chart’s performance. Thus it is important to investigate the entire run length distribution of a control chart for an in-depth understanding before implementing the chart in process monitoring. In this paper, the percentiles of the run length distribution for the double sampling (DS) X chart with estimated process parameters are computed. Knowledge of the percentiles of the run length distribution provides a more comprehensive understanding of the expected behaviour of the run length. This additional information includes the early false alarm, the skewness of the run length distribution, and the median run length (MRL). A comparison of the run length distribution between the optimal ARL-based and MRL-based DS X chart with estimated process parameters is presented in this paper. Examples of applications are given to aid practitioners to select the best design scheme of the DS X chart with estimated process parameters, based on their specific purpose.

Recent studies have shown that a double sampling (DS) scheme yields improvements in detection times of process shifts over variable ratio sampling (VRS) methods that have been extensively studied in the literature. Additionally, a DS scheme is more practical than some of the VRS methods since the sampling interval is fixed. In this paper, we investigate the effect of double sampling on cost, a criterion as important as detection rate. We study economic statistical design of the DS T2 chart (ESD DS T2) so that designs are found that are economically optimal but yet meet desired statistical properties such as having low probabilities of false searches and high probabilities of rapid detection of process shifts. Through an illustrative example, we show that relatively large benefits can be achieved in a comparison with the classical T2 chart and the statistical DS T2 charts with our ESD DS T2 approach. Furthermore, the economic performance of the ESD DS T2 charts is favorably compared to the MEWMA and other VRS T2 control charts in the literature. Copyright © 2011 John Wiley & Sons, Ltd.

This paper deals with the optimal designing of a skip-lot sampling plan of type SkSP-V by considering the double-sampling plan as the reference plan. The design parameters are determined so as to minimize the average sample number while the specified producer’s risk and the consumer’s risks are satisfied. The tables are constructed by considering the various combinations of acceptable and limiting quality levels, and an example is given for illustration purpose. The advantages of the proposed plan over the conventional double-sampling plan are also discussed.

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

In 2007, there were 33.2 million people around the world living with HIV/AIDS (UNAIDS/WHO, 2007). In May 2003, the U.S. President announced a global program, known as the President's Emergency Plan for AIDS Relief (PEPFAR), to address this epidemic. We seek to estimate patient mortality in PEPFAR in an effort to monitor and evaluate this program. This effort, however, is hampered by loss to follow-up that occurs at very high rates. As a consequence, standard survival data and analysis on observed nondropout data are generally biased, and provide no objective evidence to correct the potential bias. In this article, we apply double-sampling designs and methodology to PEPFAR data, and we obtain substantially different and more plausible estimates compared with standard methods (1-year mortality estimate of 9.6% compared to 1.7%). The results indicate that a double-sampling design is critical in providing objective evidence of possible nonignorable dropout and, thus, in obtaining accurate data in PEPFAR. Moreover, we show the need for appropriate analysis methods coupled with double-sampling designs.

Two double sampling T2 charts are discussed. They only differ in how the second sample is used to suggest to the practitioner the state of the process. An optimal method using a genetic algorithm is given for designing these charts based on the average run length (ARL). An analytical method is used to determine run length performance of the chart. Comparisons are made with various other control charting procedures. Some recommendations are given. Copyright © 2007 John Wiley & Sons, Ltd.

A common approach to the design of an acceptance sampling plan is to require that the operating characteristic (OC) curve should pass through two designated points that would fix the curve in accordance with a desired degree of discrimination. This paper presents a search procedure for the selection of double sampling inspection plans of type DSP - (0, 1) for specified two points on the OC curve, namely acceptance quality limit, producer's risk, limiting quality and consumer's risk. Selection of the plans is discussed for both the cases of fraction non-conforming and the number of non-conformities per unit.

Background: Meta-research can involve manual retrieval and evaluation of research, which is resource intensive. Creation of high throughput methods (e.g., search heuristics, crowdsourcing) has improved feasibility of large meta-research questions, but possibly at the cost of accuracy. Objective: To evaluate the use of double sampling combined with multiple imputation (DS + MI) to address meta-research questions, using as an example adherence of PubMed entries to two simple consolidated standards of reporting trials guidelines for titles and abstracts. Methods: For the DS large sample, we retrieved all PubMed entries satisfying the filters: RCT, human, abstract available, and English language (n = 322, 107). For the DS subsample, we randomly sampled 500 entries from the large sample. The large sample was evaluated with a lower rigor, higher throughput (RLOTHI) method using search heuristics, while the subsample was evaluated using a higher rigor, lower throughput (RHITLO) human rating method. Multiple imputation of the missing-completely at-random RHITLO data for the large sample was informed by: RHITLO data from the subsample; RLOTHI data from the large sample; whether a study was an RCT; and country and year of publication. Results: The RHITLO and RLOTHI methods in the subsample largely agreed (phi coefficients: title = 1.00, abstract = 0.92). Compliance with abstract and title criteria has increased over time, with non-US countries improving more rapidly. DS + MI logistic regression estimates were more precise than subsample estimates (e.g., 95% CI for change in title and abstract compliance by year: subsample RHITLO 1.050–1.174 vs. DS + MI 1.082–1.151). As evidence of improved accuracy, DS + MI coefficient estimates were closer to RHITLO than the large sample RLOTHI. Conclusion: Our results support our hypothesis that DS + MI would result in improved precision and accuracy. This method is flexible and may provide a practical way to examine large corpora of literature.

There are two types of synthetic charts for monitoring the process mean, i.e. synthetic X¯ chart and synthetic double sampling X¯ chart (SDS X¯ chart). In most applications, the process parameters, such as the in-control mean and the in-control standard deviation are usually unknown. Under such circumstances, both these process parameters need to be estimated from an in-control Phase I dataset. Thus, it is vital to study the performance of these charts when the process parameters are unknown. In this paper, the performance of two synthetic type charts with estimated process parameters will be studied. The average number of observations to signal (ANOS) criterion will be used to evaluate the performances of these charts. This study shows that the performances of synthetic type charts are significantly affected by the estimation of process parameters. Furthermore, a large number of Phase I samples is required so that the synthetic type charts with estimated process parameters will have reasonable performanc...

Objective In 1999, a survey of the health status of six rural central New York counties was performed using double sampling. The resulting impact of the methodology on health outcome prevalence estimation was assessed. Study design and setting Six counties were double sampled using methodology described by Neyman. Prevalence of health outcomes was estimated for the initial survey responders, nonresponders who subsequently responded after being offered a financial incentive, and both groups combined. Results Although both groups were similar on demographic variables, they differed significantly on several disease and health behavior prevalences. The failure to use double sampling would have resulted in overestimation of the prevalence of chronic disease by as much as 6.2% for females and 2.0% for males. Conclusion Double sampling increased the generalizability of the results from approximately 35% of the population to over 70%, and decreased the bias in the estimation of many of the health end points.

In estimating recreation visitation at the National Forest level in the US, annual counts of a number of types of visitation proxy measures were used. The intent was to improve the overall precision of the visitation estimate by employing the proxy counts. The precision of visitation estimates at sites that had proxy information versus those that did not is examined. Results show that using visitation proxy information reduces sampling needs by about 25%. Characteristics of the types of visitation proxy information that performed best and worst are discussed.

Sampling tables for the inspection of attribute quality characteristics were developed during World War II by the United States Department of Defense. In 1950, these tables led to the first military standard MIL-STD-105A which evolved into the latest version MIL-STD-105E issued in 1989. Further national and international standards emerged as derivatives of MIL-STD. On international level, the International Standards Organization (ISO) introduced the attributes sampling standard ISO 2859 which has been adopted as a national standard in many countries. The article analyzes the purpose, structure, and operation of MIL-STD-105E and of ISO 2859. Keywords: attributes sampling; sampling standard; MIL-STD-105E; ISO 2859; process proportion nonconforming; acceptable quality level; limiting quality; single sampling; double sampling; multiple sampling; switching rules; sequential sampling

A high-speed double delta sampling (DDS) circuit with pipelined structure for CMOS image sensor (CIS) is presented. Considering the low readout speed of the DDS circuit compare with correcting double sampling (CDS) circuit, We separate the main operation of DDS circuit into two steps, and run the two steps alternately in odd readout column and even readout column, which seems like the pipelined operation. Thus, the readout speed of the DDS will as twice as fast than the traditional DDS. The architecture and readout sequence of the new circuit are introduced in detail. Meanwhile simulation results indicate the proposed circuit can achieve a high speed performance.

This paper puts forward an improved channel parameter estimator based on the level crossing rate (LCR) computation and double sampling rate (DSR) signal processing, where the appropriate sampling rate is studied by the numerical computation. Subsequently, by exploiting the selected sampling rate, we can estimate both the Doppler shift and the signal-to-noise ratio (SNR) with a high accuracy. Extensive simulations explicitly show a good performance for the proposed algorithm.

This chapter addresses the issue of quality assurance for the incoming materials and the role of purchasing in preventing quality problems to crop up. Communicating specifications unambiguously and completely at the time of placing orders and choosing a vendor who has the requisite process capability to supply quality as per those specifications are the preventive strategies in quality assurance of incoming materials. Design of an optimal inspection policy to get the requisite quality protection against defectives being accepted as good with the minimum inspection cost should be the objective of incoming materials quality assurance program. Acceptance sampling plans, OC curve, AQL, and LTPD are described. In double sampling plans, the decision to accept or reject the lot can be taken after the first sample if the lot quality is very good or very bad, respectively. However, in doubtful cases, a second sample is taken, and based on combined inspection outcomes of the two samples, a decision to either accept or reject the lot is taken.

A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in a 0.5 μm CMOS technology. The measurements show 10-bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW c 3 V power dissipation.

SUMMARY Since the mid 1960s Australian forestry has benefited from small format aerial photography (SFAP) for testing new films, scales and photographic conditions; for supplementing major aerial surveys by monitoring changes on small-scale images and using this information to intensify maps, such as plantings and roads in new plantations; for achieving special effects, such as shadowless large-scale coverage to detect understorey details (e.g. disease symptoms) and for double sampling at large scales in conjunction with Global Positioning System (GPS) navigation and Geographic Information Systems (GIS) analysis to obtain quantitative data for a flexible, responsive information system. Results from early photographic and mapping trials were quickly incorporated into operational procedures which are now widely applied. Likewise, a major program utilising the special effects of large scale shadowless SFAP for disease detection has been operational for many years. However, double sampling for volume inventor...

A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.32LSB and 0.42LSB respectively, while SNDR is 56.7 dB and SFDR is 67.8 dB at an input frequency of 400 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 3.6 mW in TSMC 0.18 m CMOS 1P6M process.

A first order error feedback based noise shaping in a double sampled ADC is proposed. This topology is ideal for nanometer CMOS technology, as it obviates the need for high-gain and high output-swing op amps and fast-settling, power-hungry, and noisy reference buffers. Using a one stage op amp with a gain of 70 (i.e. 37 dB) and output swing of ±75 mV , this topology, realized in GPDK 90-nm CMOS technology, achieves an SNDR of 60 dB operating at 1 GHz (effective sample rate of 2 GHz due to double sampling) with an OSR of 32.

The double sampling (DS) X chart is superior to the traditional Shewhart X chart in detecting small and moderate process mean shifts. In general, the DS X chart is typically designed under the assumption of known parameters. Nevertheless, the actual process parameters are rarely known in practice and are usually estimated from an in-control reference Phase I sample. In this paper, we discuss the effects of parameter estimation on the performance of the DS X chart, for both the in-control and out-of-control situations. It is found that the in-control and out-of-control performances are significantly different from the case when parameters are known, especially when the shifts and the sample sizes are small. In light of these unfavorable performances, the Phase-I sample-size recommendations are provided for practitioners in designing the DS X chart with estimated parameters, so that satisfactory performances as the case with known parameters are attained.

A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18μm CMOS process technology. The simulation results show that the SFDR of the proposed full differential double sampling circuit is 81.36dB at 200MS/s. Further simulations show that the proposed full differential double sampling circuit has twice better performance than the traditional one.

Summary Disease prevalence is an important topic in medical research, and its study is based on data that are obtained by classifying subjects according to whether a disease has been contracted. Classification can be conducted with high-cost gold standard tests or low-cost screening tests, but the latter are subject to the misclassification of subjects. As a compromise between the two, many research studies use partially validated datasets in which all data points are classified by fallible tests, and some of the data points are validated in the sense that they are also classified by the completely accurate gold-standard test. In this article, we investigate the determination of sample sizes for disease prevalence studies with partially validated data. We use two approaches. The first is to find sample sizes that can achieve a pre-specified power of a statistical test at a chosen significance level, and the second is to find sample sizes that can control the width of a confidence interval with a pre-specified confidence level. Empirical studies have been conducted to demonstrate the performance of various testing procedures with the proposed sample sizes. The applicability of the proposed methods are illustrated by a real-data example.

Sampling plans are used widely in the electronic industry, especially for electronic components such as integrated circuits and capacitors. A double sampling plan involves less items inspected per lot than a single sampling plan considering the same protection level. This paper presents a developing model to compute the optimum design for a double sampling plan. This model is demonstrated with an application. Also, a sensitivity analysis is carried out to show the effect of change of various parameters on the solution.

Electronics readout based on multi-correlated double sampling (multi-CDS) have been designed in the past for spectroscopy applications using multi-element semiconductor detectors. This technique can be employed when a synchronism signal is available. We present a new integrated circuit, based on multi-CDS, which can be used also for the detection of random events in absence of synchronism signal. A prototype of the circuit has been designed and produced. The first results of the experimental characterization are presented here.

The possibility of implementing the double-sampling (DS) techinque in infinite impulse response (IIR) first- and second-order switched-capacitor (SC) decimators is considered. The DS-SC circuits that result are designed using the same procedure as standard IIR decimators, and only a different SC implementation results with a reorganized clock phasing. The main advantage is that the time allowed for the op-amps to settle can be equal to the output sampling period rather than one half of it. Using the proposed DS decimators allows the design of high-frequency SC filtering systems (an antialiasing SC decimator filter and a 'core' DS-SC filter) where the op-amp speed requirements are the same in each block. >

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not introduce a detrimental extra factor into the loop gain. It allows the use of efficient design methods for DeltaSigma ADCs.

We developed a 10.7-MHz intermediate frequency (IF) bandpass discrete-time (DT) 4th -order 4-bit ΔΣ modulator for AM/FM car radio tuners. Using direct feed-forward and double sampling, we have achieved a dynamic range (DR) of 112 dB in the 3-kHz AM bandwidth (BW) and a DR of 94 dB in the 200-kHz FM BW. The modulator occupies 3 mm2, in 0.15 μm CMOS technology, and draws 63 mA of current.

Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon (Das et al., 2006), (Kim et al., 2005), (Worm et al., 2005), So far, reliable operation of existing link checkers - double sampling flip-flops or code-based - is not ensured over the whole range of bit error rate. Therefore, bit error rates where the checker reliability is poor are avoided either by worst-case characterisation of the link error rate (such as for double sampling flip-flops), or by constraining the operating point controller to avoid such regions (such as for code-based checkers). This paper proposes a novel checker architecture that bridges the gap between low overhead and high robustness over the whole error rate range. Specifically, the paper shows how to combine optimally double sampling flip-flops with a code-based checker (in point of reliability). The resulting checker enables simple, efficient, and reliability-agnostic operating point control policies

A single-amplifier double-sampling second-order /spl Delta//spl Sigma/ ADC with 5-level quantization is implemented in 90nm CMOS. To alleviate the capacitor mismatch issues in double sampling techniques, a single capacitor method is introduced, achieving 63dB peak SNDR and 66dB DR in a 1.94MHz bandwidth while consuming 1.2mW from a 1.2V supply.

This paper presents a double-sampling switched-current integrator which is used to implement a second-order sigma-delta modulator. The effects of the non-ideal behavior of switched-current circuits can be summarized in a signal-dependent and independent error. Leaky integrators are the result of the signal-dependent error. It is shown that the double-sampling integrator can reduce the leak factor to the half.

This paper presents SIMULINKr modeling of the non-idealities of a bandpass sigma-delta modulator which are appropriate for behavioral simulation. Such non-idealities include clock random jitter, periodic timing-skew, op-amp non-idealities parameters (DC gain, slew-rate, gain-bandwidth, saturation voltage, capacitor mismatch and noise), and also the complete modulator noise analysis. Such modeling will be based on a real design example of a 4th-order switched-capacitor (SC) bandpass sigma-delta modulator with double sampling. Follow the top-down design manner, the behavioral simulation targets the necessary design specifications for various building blocks.

The performance of double-sampling sigma-delta A/Ds can suffer due to capacitor mismatch as well as uneven clock phases. Improving the resulting SNR is essential. This paper presents a method that uses DSP techniques to filter out the mismatch. Simulation results of applying an adaptive LMS filter to a fourth-order double-sampling bandpass sigma delta modulator are presented that show an improvement in SNR of more than 30 dB.