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A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.

Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with stacked tunneling layer were studied in this work. The programming speeds of poly-Ge tri-gate JL flash device with GeOx/Al2O3/SiO2 tunneling layer are faster than those with GeOx/Al2O3 or GeOx/SiO2 ones, thanks to the modified electric field in the tunneling layer. Better retention characteristics are also achieved due to a larger barrier height and physical thickness, because Ge diffusion is effectively suppressed by adding an Al2O3 between GeOx and SiO2, which can improve the quality of tunneling layer. A poly-Ge CT flash device fabricated with low-temperature process is promising for embedded memory in Ge CMOS or 3D IC.

The operation characteristics of polycrystalline Si (poly-Si) gate-all-around (GAA) junctionless (JL) charge-trapping (CT) flash memory devices with the Zr-based stacked trapping layer were studied in this work. Devices with the Si3N4/ZrO2 stacked trapping layer show enhanced erasing speeds and comparable retention characteristics in comparison to Si3N4/HfO2 due to many shallow energy traps and smaller valance band offset in the ZrO2 layer. By inserting Al2O3 between Si3N4 and ZrO2 trapping layer, the retention and endurance characteristics are improved. The erasing speed can be further improved by a Zr-rich oxide layer near the tunneling oxide since the energy barrier can confine more injected electrons near the tunneling oxide. The retention characteristic can be improved without sacrificing the erasing speed because some of the shallow traps can be passivated by NH3 plasma treatment on ZrO2. Hence, the ZrO-based stacked trapping layer is very promising for the poly-Si GAA JL CT flash devices for nonvolatile memory applications.

In this study, the device characteristics of dual-gate GaN high-electron-mobility transistors (HEMTs) were determined. The research investigated an enhancement-mode (E-mode) GaN HEMT with a second gate connected to the source and located between the main gate and drain. Two dual-gate GaN HEMTs with different second-gate designs, using Schottky or metal–insulator–semiconductor (MIS) contacts, were simulated and fabricated, and the direct current of the devices was investigated. In device simulation, p-GaN gates were used to achieve E-mode operation in HEMTs. Technology computer-aided design (TCAD) simulation indicated that the saturation drain current (ID, sat) of devices with Schottky and MIS second gates was 88% and 38% lower than that of a single gate structure, while increasing on resistance (Ron) by 31% and 8%, respectively. In device fabrication, a Schottky and MIS second gate were respectively added to an E-mode p-GaN gate HEMT and an E-mode recesses-gate GaN MIS-HEMT. Compared with single-gate structures, the devices with a Schottky and MIS second gates reduced ID, sat by 75% and 32%, respectively, while increasing Ron by 25% and 6%, respectively. The measured electrical characteristics indicate the same trend obtained from TCAD simulation: The dual-gate design can improve the short-circuit capability of GaN HEMTs by reducing the ID, sat under on-state and high-current conditions.

A single-crystal-island (SCI) technique is demonstrated using low thermal budget pulse laser process to fabricate single-crystal islands for monolithic 3D back-end-of-line (BEOL) FinFET circuits. The single-crystallinity are verified with SECCO etch, HREM, TEM, and EBSD. BEOL FinFETs fabricated in the designed single-crystal Si islands exhibit excellent electrical performance and low intra-island variability. To mitigate the effects of island-to-island device variation due to random island crystal orientations, crystal-orientation-tolerant voltage regulator is further proposed by allocating power gating (PG) cells among multiple Si islands, and 42% power noise suppression can be achieved.

This paper demonstrates the first Monolithic 3D+-IC based Compute-in-Memory (CiM) Macro performing massively parallel beyond-Boolean operations targeting database and machine learning (ML) applications. The proposed CiM technique supports data filtering, sorting, and sparse matrix-matrix multiplication (SpGEMM) operations. Our system exhibits up to 272x speedup and 151x energy savings compared to the ASIC baseline.

For the first time, ultrafast laser annealed BEOL gate-all-around (GAA) transistor and FeFET memory were demonstrated with monolithic 3D near-memory-computing (NMC) circuit. The GAA MOSFETs employing ultrafast picosecond visible laser dopant activation exhibit record-high Ion (nFETs=407 uA/um, pFETs=345 uA/um). The BEOL FeFETs memory exhibits large memory window ΔV th = 1.2V, more than 106 cycle endurance. Moreover, the 3D stackability of the GAA MOSFETs and FeFET memory bit cell enable reduces the area of the NMC circuitry and improve the readout throughput.

In this work we propose a first attempt in the fabrication of a family of monolithic GaN-based quaternary multi-value logic gates (MVL), including QNOT, QNOR, and QNAND in a process flow compatible with enhancement mode (E-mode) power HEMT (BV > 650 V). Integration of MVL with GaN power HEMTs increases logic-state density and allows for the design of smart gate drive circuits with reduced switching loss and ringing when compared to circuits using discrete devices. Using TCAD and SPICE device models calibrated against experimental data we demonstrate the functionality of a quaternary inverter with noise margins NML and NMH above 60% and 50% of the logic state voltage range, respectively. Quaternary logic gates show an average reduction of 27% in area utilization when compared to binary logic gates. Additionally, the layout of a quaternary 16-bit DEMUX circuit is projected to occupy 22.5% less area than its binary equivalent. The application of quaternary MVL to digital control circuits for GaN power HEMTs is expected to reduce total circuit area and consume less power than a binary counterpart.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 &deg, C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 &micro, A/&micro, m (n-type) and 297 &micro, m (p-type) @ Vth &plusmn, 0.8 V, and higher Ion/Ioff (&gt, 105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(&Omega, )-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

A large-area and scalable monolayer TMD is feasible to employ in monolithic 3D image sensor scheme. For the first time, we represents a prototype $\mathrm{MoS}_{2}$ phototransistor array with ultrahigh responsivity $(> 10^{3}\ \mathrm{A}/\mathrm{W})$ and tunable photogain (10 2 ~10 5 ) which can be directly implemented on a CMOS circuit connected with BEOL fine-pitch vertical interconnects. Electric gate pulse modulation mitigates photo gating (PG) and persistent photoconductance (PPC) effects from layered semiconductor interface. Both three-order-of-magnitude improvements of response speed and fine-pitch vertical interconnects empower block-level compressive sensing circuits and global image-signal processing for gain control and data compression.

For the first time, below 400°C-fabricated poly-Si MOSFETs and 6T -SRAM fabrication process was demonstrated on polyimide (PI) substrate for flexible and transparent monolithic 3DIC. Key enablers are 400–900 nm transparent laser-stop layer (LsL), laser-crystallized/CMP-thinned poly Si channel and pulse UV-laser S/D activation. These advanced low thermal budget fabrication technologies enable stackable polySi MOSFETs on flexible 6” -wafer-scale PI substrate with high device uniformity $(\mathrm{V}_{\mathrm{th}}$ ‘SS~16.2%/16.6%) and bending stability $(\mathrm{V}_{\mathrm{th}}/\mathrm{SS}\sim 4.2\%/9.8\%)$ after cycle-bending at radius of 10mm. Such CMOS compatible technologies envision flexible 3D heterogeneous integration of circuits/optical sensors for human-skin adaptable Internet of Things (IoT) chips.

The SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO2 and Si3N4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.

Selenium (Se) is one of the potential candidates as photodetector because of its outstanding properties such as high photoconductivity (∼8 × 104 S cm–1), piezoelectricity, thermoelectricity, and nonlinear optical responses. Solution phase synthesis becomes an efficient way to produce Se, but a contamination issue that could deteriorate the electric characteristic of Se should be taken into account. In this work, a facile, controllable approach of synthesizing Se nanowires (NWs)/films via a plasma-assisted growth process was demonstrated at the low substrate temperature of 100 °C. The detailed formation mechanisms of nanowires arrays to thin films at different plasma powers were investigated. Moreover, indium (In) layer was used to enhance the adhesive strength with 50% improvement on a SiO2/Si substrate by mechanical interlocking and surface alloying between Se and In layers, indicating great tolerance for mechanical stress for future wearable devices applications. Furthermore, the direct growth of Se NWs...

Recent monolithic 3-D integrated-circuit (3D-IC) technology tends to induce stronger driving capability in pMOS transistors, compared to that obtained using existing processes. Thus, conventional 6T SRAMs suffer degradation in access speed and write margin when used in monolithic 3D-ICs. This letter proposes a dual-split-controlled 4P2N (DSC-4P2N) SRAM with corresponding read and write assist schemes capable of providing a larger cell read current and higher write margins compared to 4N2P SRAMs implemented in monolithic 3D-ICs. The proposed DSC scheme improves $4.8\times $ in read stability compared to 4P2N SRAM without DSC. A fabricated DSC-4P2N SRAM in monolithic 3D-IC was shown to outperform the previous 6T SRAMs.

A Ge0.955Sn0.045 nMOSFET with a record high mobility of 440 cm2/V $\cdot $ s is demonstrated in this letter by a gate-first process. By low-temperature chemical vapor deposition, high-quality GeSn films were epitaxially grown. The ambipolar leakage is effectively suppressed by the low-thermal-budget microwave annealing (MWA) step. Furthermore, the peak mobility in the device after the MWA step is enhanced by a factor of two compared with those after rapid thermal annealing. This can be attributed to the weaker Coulomb scattering at the oxide interface after the MWA step, suggesting that MWA is effective for dopant activation and a better oxide interface quality at the same time.

This letter demonstrates the excimer laser crystallization (ELC) of germanium (Ge) thin films with the recessed-channel (RC) structure for high-performance p-channel Ge thin-film transistors (TFTs). Using ELC, large longitudinal grains with a single perpendicular grain boundary (GB) in the center of the recessed region were formed. This can be attributed to the lateral grain growth from un-melted Ge solid seeds in the thick region toward the complete melting recessed region during ELC. Consequently, the proposed p-channel RC-ELC Ge TFTs possessing large longitudinal grains without the perpendicular GB in the channel region exhibited a superior field-effect hole mobility of 447 cm2V−1s−1 with minor performance deviation.

For the first time, below 400°C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I on /I off ratio (~108) with low I off (pFETs

In this research, Finite Element Method (FEM) is used to simulate transient thermal conduction in the monolithic three-dimensional integrated circuit (3DIC) with a novel location-controlled-grain (LCG) technique. Through this method, the impact of laser flux, amorphous Si thickness and interlayer dielectric (ILD) thickness on that model can be investigated. Furthermore, with the assistance of thermal damage simulation, we can utilize the optimal process parameters in this state-of-the-art technique to accelerate the development of advanced semiconductor technologies.

An inductively coupled plasma (ICP) process was used to synthesize transition metal dichalcogenides (TMDs) through a plasma-assisted selenization process of metal oxide (MOx) at a temperature as low as 250 °C. In comparison with other CVD processes, the use of ICP facilitates the decomposition of the precursors at low temperatures. Therefore, the temperature required for the formation of TMDs can be drastically reduced. WSe2 was chosen as a model material system due to its technological importance as a p-type inorganic semiconductor with an excellent hole mobility. Large-area synthesis of WSe2 on polyimide (30 × 40 cm2) flexible substrates and 8 in. silicon wafers with good uniformity was demonstrated at the formation temperature of 250 °C confirmed by Raman and X-ray photoelectron (XPS) spectroscopy. Furthermore, by controlling different H2/N2 ratios, hybrid WOx/WSe2 films can be formed at the formation temperature of 250 °C confirmed by TEM and XPS. Remarkably, hybrid films composed of partially reduced...

It is widely known that thinner Si substrate is the main path for lower $/Watt HIT solar cells due to improved charge collection, reduced bulk and total recombination, and fewer raw material consumption (Panasonic, IEEE Journal of Photovoltaics., vol. 4, p. 96, 2014). Nonetheless, thin substrates always lead to low mechanical stability and wafer breaking. In this work, spray coated 50 nm graphene layer is used as the back electrode in Si HIT solar cells to enhance the mechanical stability. With the incorporation of graphene as the back electrode in Si HIT solar cells, remarkable improvements in substrate mechanical strength are achieved. Without the degradation of HIT solar cell efficiency, hardness is increased nearly twofold from 902 to 1747 HV. The Young's modulus is increased from 93.9 to 140.1 GPa while the ultimate tensile strength is increased from 96.71 to 273.68 MPa. Low-cost chemical exfoliation method and low-temperature (150 °C) spray coating method have been employed for the preparation and deposition of thin graphene back electrode, respectively. In addition, unlike the graphene as the substitute for ITO in OLED applications, the graphene strengthened thin silicon substrate technology here imposes no additional constraint on the graphene electrode transparency since it is used as a back electrode. We, thereby, believe that our proposed method is effective for attaining higher efficiency and lower $/Watt thin Si HIT solar cell technology with enhanced mechanical strength.

Three-dimensional sequentially stackable high- $k$ /metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and postsurface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 $\mu \text{A}/\mu \text{m}$ ), and $I_{{\mathrm{\scriptscriptstyle {on}}}}/I_{\mathrm{\scriptscriptstyle {OFF}}}$ ratio ( $> 10^{5})$ . Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low $V_{\mathrm {dd}}$ (0.6 V) operable inverter.

Designing an efficient emitter design is an important step for achieving a highly efficient TPV conversion process. Wavelength-selective emissivity, spectra match between the emitter and TPV cells, and high thermal stability are three main characteristics that must be considered before implementing the emitter. In this work, an indium tin oxide (ITO)/sapphire emitter structure is investigated for TPV application over the temperature range from 200°C to 1000°C. A 1-µm-thick ITO layer is deposited on a 650-µm-thick sapphire substrate. In addition, 50-nm-thick SiO2 is deposited on top of the ITO to enhance the performance of emitter at high temperatures. High-temperature emissivity and absorptivity measurement of the emitter samples are obtained using FTIR and a Hitachi U-4100 spectrophotometer, respectively. The resultant SiO2/ITO/sapphire/stainless-steel planar emitter structure has selective emission with high emissivity of ∼0.8 in the 1–1.6 µm wavelength regime at 1000°C. This emission range lies at the bandgap edge of silicon TPV cells and thus can be used to harness the true potential for making a low-cost thermophotovoltaic system.

For the first time, ultra-low power ferroelectric FinFET-based monolithic 3D+-IC technology was demonstrated for near memory computing (NMC) circuit. Key enablers are ICP-SiO 2 interfacial layer, doped hafnia ferroelectric gate dielectric layer (HfZrO 2 ), and far-infrared laser activation. The proposed stackable 3D NC-FinFETs thus fabricated exhibit record-low sub-threshold swing (NC-nFinFET: 45mV/dec and NC-pFinFET: 50mV/dec) and high I on /I off (>106) that enable ultra-low power operation $(\mathrm{V}_{\text{DD}}=100\text{mV})$ of CMOS inverter and SRAM. Moreover, above mentioned features of NC-FinFETs and the differential output of SRAM readout enable 50+% area reduction in the near-memory computing circuitry.

A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2 . The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing ( $385\ \mu \mathrm{A}/\mu \mathrm{m}$ ), and high I on /I off (>106). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 °C.

We report heterogeneously integrated sub-40nm epi-like monolithic 3DIC with vertical ReRAM and memory computing (NMC) circuit. High driving current multi-channel UTB-MOSFETs (3.3/1.4 mA$/\mu \mathrm {m}$ for N/P FETs) was realized by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO 2 far-infrared laser annealing (CO 2 -FIR-LA) activation technologies that enable driving 20nm 4-layer vertical ReRAM (Set/Reset $ \lt 1.2\mathrm {V}/1.8\mathrm {V}$, 3-bits/cell). Furthermore, the ultra-low threshold voltage of NC-FinFETs and the differential output of SRAM readout enable 50 +% area reduction in the near-memory computing circuitry. The unique TSV-free monolithic $3\mathrm {D} ^{+}$ IC process provides the superiority in 3D hetero-integration to realize low cost, small footprint, fully functionalized 3D IoTs chip.

We present a novel 3D-SRAM cell using a Monolithic 3D integration (M3D-IC) technology for realizing both robustness and In-memory Boolean logic compute support. The proposed two-layer design makes use of additional transistors over the SRAM layer to enable assist techniques as well as provide logic functions (such as AND/NAND, OR/NOR, XNOR/XOR) without degrading cell density. Through analysis, we provide insights into the benefits provided by three memory assist and two logic modes and evaluate the energy efficiency of our proposed design. Assist techniques improve SRAM read stability by 2.2x and increase the write margin by 17.6%, while staying within the SRAM footprint. By virtue of increased robustness, the cell enables seamless operation at lower supply voltages and thereby ensures energy efficiency. Energy Delay Product (EDP) reduces by 1.6x over standard 6T SRAM with a faster data access. Transistor placement and their biasing technique in layer-2 enables In-memory bitwise Boolean computation. When computing bulk In-memory operations, 6.5x energy savings is achieved as compared to computing outside the memory system.

We report on the fabrication of a robust and flexible transparent electrode to replace costly and fragile indium tin oxide (ITO) used in flexible Cu(In,Ga)Se2 solar cells, composed of an aluminum doped zinc oxide (AZO)/Ag-nanowires/aluminum doped zinc oxide (AZO) (AAA herein) sandwich structure. The Ag-NWs networks form low-resistance, long-range pathways throughout the electrode that are able to maintain efficient charge carrier collection and extraction after strenuous mechanical bending. The improved durability of the AAA electrode enables our CIGS solar cells to maintain ∼95% of their initial power conversion efficiency, following 1000 bending cycles. In comparison, devices fabricated using AZO and ITO electrodes are only able to maintain ∼57 and ∼5%, respectively, due to crack formation and delamination of the films. This AAA sandwich structure electrode could therefore serve as a high-performance electrode for numerous flexible optoelectronic applications.

Display Omitted In-situ doped poly-Si on vertically stacked JL flash memory devices are studied.Devices with in-situ doped (ISD) poly-Si channel show a large disturb-free window.Fast programming/erasing speeds, good retention and endurance are obtained.ISD poly-Si is promising for future three-dimensional CT flash device. Effects of in-situ doped (ISD) polycrystalline silicon (poly-Si), which serves as the source, drain and channel, on vertically stacked junctionless (JL) charge-trapping (CT) flash memory devices are investigated for the first time. The vertically stacked JL devices formed by ISD poly-Si channel show minimized program disturb with a large disturb-free window of 4.5V even when a low program-inhibit voltage (Vinhibit) of 6V is applied. It can be attributed to the fast programming speed of ISD JL device. Fast programming/erasing (P/E) speeds, good retention and endurance characteristics are also obtained. Therefore, ISD poly-Si is promising for future three-dimensional (3D) CT flash integration.

In this work, enhanced broadband solar spectrum absorption and solar-thermal conversion efficiency (~ 8%) has realized and reported by Au-decorated CuInS 2 nanoparticles, namely Au@CIS NPs. The morphologies, compositions and absorptions were characterized by high resolution transmission electron microscopy (HR-TEM), UV–vis spectrometer and Finite-Difference Time-Domain (FDTD) numeric methods. The Au@CIS NPs shows a distinguished absorption perfectly matching AM1.5 G solar spectrum, compared with pure Au, CIS and CIS–Au mixture nanoparticles (NPs) owing to near field plasmonic-assisted effect. In addition, the Au@CIS NPs proves its practical applications on selective distillation in non-polar solvent systems, for which the selective distillation of methylcyclohexane from toluene as an example was demonstrated. The approach can evoke future developments of plasmonic-assisted heterostructure in nanoscale for thermal solar energy harvesting application.

A reactive mold-assisted chemical etching (MACE) process through an easy-to-make agarose stamp soaked in bromine methanol etchant to rapidly imprint larger area micro- and nanoarrays on CIGS substrates was demonstrated. Interestingly, by using the agarose stamp during the MACE process with and without additive containing oil and triton, CIGS microdome and microhole arrays can be formed on the CIGS substrate. Detailed formation mechanisms of microstructures and the chemical composition variation after the etching process were investigated. In addition, various microand nanostructures were also demonstrated by this universal approach. The microstructure arrays integrated into standard CIGS solar cells with thinner thickness can still achieve an efficiency of 11.22%, yielding an enhanced efficiency of ∼18% compared with that of their planar counterpart due to an excellent absorption behavior confirmed by the simulation results, which opens up a promising way for the realization of high-efficiency micro- or nanostructured thin-film solar cells. Finally, the complete dissolution of agarose stamp into hot water demonstrates an environmentally friendly method by the mold-assisted chemical etching process through an easy-to-make agarose stamp.

Luminescent down-shifting (LDS) phenomenon has been employed to enhance the HIT solar cell efficiency. The efficiency and J SC are increased by 2.3% and 11.5% respectively. External quantum efficiency (EQE) data supports our claim.

A facile wet soaking process by immersing a CIGS thin film in a mixed aqueous solution, containing gallium trichloride and thioacetamide at 80 °C for a few tens of seconds, was proposed to reduce the existence of defects in the CIGS absorption layer which can be confirmed by the temperature dependence of the open-circuit voltage (Voc). The depth profiles of X-ray photoelectron spectroscopy (XPS) results indicate that the gallium (Ga) concentration increases during the short wet soaking time, resulting in a widening of the band gap near the surface region. The enhanced carrier lifetime attributed to the Ga-induced defect reduction during thermal treatment of device fabrication was evaluated by time-resolved photoluminescence (TRPL) spectroscopy. With wet and light soaking processes, Voc, short circuit current (Jsc) and fill factor (F.F.) can be increased, yielding a significant enhancement in cell efficiency from ∼1% to ∼6.4%. We believe that this fast, simple and effective method can further stimulate the development of CBD-Zn(O,S)/post-selenization CIGS solar cells toward commercialized thin film photovoltaics.

This paper presents the first monolithic 3D vertical cross-tier computing-in-memory (CIM) SRAM cell fabricated using low cost TSV-free FinFET-based 3D+-IC technology. The 9T 3D CIM SRAM cell is able to compute NAND/AND, OR/NOR and XOR/XNOR operations within a single memory cycle. We fabricated stackable multi-fin single-grained Si FinFET using low thermal-budget CO 2 far-infrared laser annealing (FIR-LA) for activation and self-aligned silicide. The proposed device achieved high Ion (320 μA/μm (n-FET) and 275 μA/μm (p-FET)) and high I on /I off (>107). The proposed scheme enables the fabrication of energy and area efficient circuits for cost-aware intelligent IoT devices. For proposed 9T CIM SRAM cell, the monolithic 3D device reduces area overhead by 51%, compared to the 2D version, thanks to the stacking of three additional transistors above the 6T SRAM cell.

A p-a-SiC:H window layer was used in amorphous Si thin film solar cells to boost the conversion efficiency in an indoor lighting of 500 lx. The p-a-SiC:H window layer/p-a-Si:H buffer layer scheme moderates the abrupt band bending across the p/i interface for the enhancement of VOC, JSC and FF in the solar spectra of short wavelengths. The optimized thickness of i-a-Si:H absorber layer is 400 nm to achieve the conversion efficiency of ~9.58% in an AM1.5 G solar spectrum. However, the optimized thickness of the absorber layer can be changed from 400 to 600 nm in the indoor lighting of 500 lx, exhibiting the maximum output power of 25.56 μW/cm2. Furthermore, various durability tests with excellent performance were investigated, which are significantly beneficial to harvest the indoor lights for applications in the self-powered internet of thing (IoT).

The additional enhanced in conversion efficiency of the heterojunction with intrinsic thin-layer (HIT) silicon solar cell by using plasmonics scattering of indium nanoparticles (In NPs) was experimentally demonstrated. The conversion efficiency of 17.15% for the HIT solar cell with In NPs was obtained, compared to that of 16.63% for HIT solar cell without In NPs.

External light trapping has been proposed as an alternative to internal light trapping. The advantage is that the electrical and optical characteristics can be designed separately. This enhances the degree of improvement that nano-photonics can contribute to the solar cell efficiency and J SC . In this work, we use diffuse trench reflectors with down-conversion polymer to demonstrate the concepts of a low-cost, widely applicable scheme for the external light trap. A >50% enhancement of the J SC can be observed with proper designs and configurations. The proposed external light trap can be applied to nearly all thin-film solar cell technologies since the external optical components do not affect the electrical diode characteristic of the solar cells. The efficient external light trap is attributed to the high reflectance of the disuse mirror and its wide-angle diffractions, optical confinement due to the trench reflector, and the additional short-wavelength spectral enhancement by the down-conversion mechanism.

In this work, HIT solar cell is incorporated with the luminescent down-shifting (LDS) mechanism for the incident solar spectrum. The heterojunction with intrinsic thin-layer(HIT) solar cell is highly efficient, low temperature (200°C), low cost, and highly symmetrical device. Nevertheless, the carrier collection efficiency is low for the short wavelength solar photons due to the surface recombination. Here, a thin phosphor layer is spray coated on the top of HIT solar cells for the luminescent down-shifting of high energy photons and thus enhanced external quantum efficiency (EQE) for the device for A=300nm-450nm is observed.

In this work, we develop the process flow for nano-imprinted metamaterial patterns for perovskite solar cell light trapping. Nanoimprint can be scaled for large-area photovoltaics at low cost, compared to conventional lithography techniques. While conventional grating is normally underneath the solar cell active layers, the degraded electrical characteristic can be a problem. On the other hand, the external light trapping separates the electrical and optical designs and, therefore, it is more promising for complex photonic management without sacrificing the diode characteristics. We demonstrate the concept by perovskite solar cells with metamaterial patterns. Imprinting a deeper metamaterial pattern is suggested to enhance the far field effect for further efficiency improvement.

Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

Indoor utilization of emerging photovoltaics is promising; however, efficiency characterization under room lighting is challenging. We report the first round-robin interlaboratory study of performance measurement for dye-sensitized photovoltaics (cells and mini-modules) and one silicon solar cell under a fluorescent dim light. Among 15 research groups, the relative deviation in power conversion efficiency (PCE) of the samples reaches an unprecedented 152%. On the basis of the comprehensive results, the gap between photometry and radiometry measurements and the response of devices to the dim illumination are identified as critical obstacles to the correct PCE. Therefore, we use an illuminometer as a prime standard with a spectroradiometer to quantify the intensity of indoor lighting and adopt the reverse-biased current-voltage (I-V) characteristics as an indicator to qualify the I-V sampling time for dye-sensitized photovoltaics. The recommendations can brighten the prospects of emerging photovoltaics for indoor applications.

In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f T) and maximum oscillation frequencies (f max) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f T and f max are around 25 GHz and 30 GHz, respectively. The high f T and f max as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications.

Nanostructured photovoltaics has attracted an enormous amount of attention in recent years owing to its potency for significant device performance enhancement over the conventional technologies. Nonetheless, conventional fabrication approaches for nanostructured scaffolds rely on glass or silicon substrates which are costly, brittle and have limited scalability. Meanwhile, rational design guidelines for optical and electrical performance optimization of solar cells are of urgent need for their practical applications. In this work, flexible and quasi-ordered three-dimensional (3-D) nanospike (NSP) arrays are fabricated on a reasonable large scale with well controlled geometry. Systematic investigations by experiments discovered that photovoltaic devices based on NSPs with optimal geometry can accommodate the trade-off between optical absorption and electrical performance, demonstrating a power conversion efficiency of 7.92%, which is among the highest efficiency reported for single junction a-Si:H solar cells on a flexible substrate. Furthermore, we have demonstrated the superior omnidirectional device performance by utilizing such a 3-D NSP. This unique feature is of paramount importance for practical photovoltaic applications.

A comparative study of indium-tin-oxide (ITO) nanowhiskers (NWhs) and thin films as transparent conductors in the terahertz frequency range are conducted. We employ both transmission-type and reflection-type terahertz time-domain spectroscopies (THz-TDTS and THz-TDRS) to explore the far-infrared optical properties of these samples. Their electrical properties, such as plasma frequencies and carrier scattering times, are analyzed and found to be fitted well by the Drude-Smith model over 0.1-1.4 THz. Further, structural and crystalline properties of samples are examined by scanning electron microscopy and X-ray diffraction, respectively. Non-Drude behavior of complex conductivities in ITO NWhs is attributed to carrier scattering from grain boundaries and impurity ions. In ITO thin films, however, the observed non-Drude behavior is ascribed to scattering by impurity ions only. Considering NWhs and thin films with the same height, mobility of the former is ~ 125 cm2V-1s-1, much larger than those of the ITO thin films, ~ 27 cm2 V-1 s-1. This is attributed to the longer carrier scattering time of the NWhs. The dc conductivities ( ~ 250 Ω-1 cm-1) or real conductivities in the THz frequency region of ITO NWhs is, however, lower than those of the ITO thin films ( ~ 800 Ω-1 cm-1) but adequate for use as electrodes. Partly, this is a reflection of the much higher plasma frequencies of thin films. Significantly, the transmittance of ITO NWhs ( ≅ 60%-70%) is much higher ( ≅ 13 times) than those of ITO thin films in the THz frequency range. The underneath basic physics is that the THz radiation can easily propagate through the air-space among NWhs. The superb transmittance and adequate electrical properties of ITO NWhs suggest their potential applications as transparent conducting electrodes in THz devices.

For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D+-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D+ UTB-MOSFETs (600μA/282μA@VG= ± 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO 2 far-infrared laser annealing (CO 2 -FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset

A footprint-efficient and power-saving BEOL compatible 3D+IC carrying monolithic 3D stackable FinFETs (3D+ FinFETs) and W interconnect were demonstrated by low thermal budget laser spike anneal technology (Tsub 7) 3D+ FinFETs exhibit steep subthreshold swing (S.S.∼65mV/dec.), record high driving current (I on per W Eff (W Eff =2H Fin +W Fin ): 386 μA/μm (n-type) and 352μA/μm (p-type)), and high I on /I off (>107), envisioning next generation low-cost heterogeneously integrated IoTs and wearable electronics.

A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer ( 20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (T sub 200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at V DD =0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.

Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low Ioff and high Ion operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm2) under 450 lux indoor illumination, envisions self-power and low cost 3D+IC for internet of things.

We investigate the performance of amorphous Si (a-Si) solar cells fabricated with Inductively Coupled Plasma (ICP) deposition technique. The ICP system produces a-Si films with low defect density ( 3 × 10 15 cm − 3 ) , resulting in a conversion efficiency of 9.6%. Deep level transient spectroscopy (DLTS) reveals that hole carriers trapped at defects near the valence band edge delocalize at 130 K; while trapped electrons can only be emitted into the conduction band near room temperature. Spectrally resolved DLTS study further indicates that light soaking enhances the emission rate of the tapped electrons near the conduction band edge while reduces the transition moments from the hole-trapping defect levels to the conduction band. The combined effects and light soaking-induced defects are responsible for the degradation of a thin film solar cell by light soaking.

A p-type polycrystalline Ge (poly-Ge) film processed by UV and CO2 laser annealing reduces the hole concentration from 6 × 1018 to 2 × 1016 cm−3, accompanied by poly-grain growth. The decrease in hole concentration arises from the defect annealing using a CO2 laser, as demonstrated by the changes in the work function, that is, the valence-band maximum (VBM). The laser processes reduce the thermal budget for the fabrication of an enhancement-mode poly-Ge nMOSFET, which has a I on/I off ratio of 5 × 103, a V th of 2 V, and a subthreshold swing of 250 mV/dec., and will be potential fabrication methods for monolithic 3D integrated circuits in the future.