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This work presents a D-band monostatic radar system operating from 144.6 to 161 GHz, which is placed inside a 3-D-printed low-cost case with a built-in lens to boost the antenna (ANT) directivity. The monolithic microwave integrated circuit (MMIC) is manufactured in a 130-nm BiCMOS process and includes a compact transceiver architecture consisting of an oscillator, a diode-based mixer, and an on-chip antenna. The implemented topology allows to significantly improve the signal-to-noise ratio and features a built-in self-test (BIST) structure with the possibility to provide on-chip antenna characterization using power sensors in combination with a directional coupler. Housed inside the robust printed package, the MMIC has only dc and baseband frequency connections, which offers ease of handling and poses the low-cost potential for a variety of applications. The complete transceiver chip consumes only 84.7 mA from a 3.3-V supply and its size is 1964 μm x 1448 μm. Together with the package the sensor measures a size of 42.2 mm x 42.2 mm x 45.7 mm.

A low phase noise, wide tuning range 20GHz magnetic-coupled Hartley-VCO fabricated in a 28nm CMOS technology is presented and targeted for 77/79GHz radar applications. The VCO is designed and optimized for low phase noise and large frequency tuning range by using a Hartley-VCO architecture. A wide tuning range of 2.2GHz and a best phase noise of -113.8dBc/Hz@1MHz have been achieved. To the best of authors’ knowledge, this is the best VCO phase noise presented in an advanced CMOS technology. Furthermore, the VCO shows an excellent pushing performance of less than ± 80 MHz $/V$ due to the implemented current source on top of the VCO core. The VCO core has an area of 0.038 mm $^{2}$ and consumes 50mA from a 1.8V supply.

This work presents the design of a power amplifier (PA) with an AC-coupled common-emitter and common-base stage in a 130 nm SiGe BiCMOS technology. The amplifier operates in the D-band and consists of two driving stages followed by an output power stage. At 143 GHz a small signal gain of 39.8 dB and a maximum saturated output power (P SAT ) of 16 dBm is achieved. The PAE peak value is 5.4 %, while the chip draws 220 mA from a 3.3 V power supply. Including pads the chip consumes an area of 0.66 mm2. To the best of the authors’ knowledge this is the highest value for P SAT reported in this frequency range using silicon-based technologies.

In this paper a low-power Low Noise Amplifier (LNA) with ultra broad bandwidth is presented. We propose a novel circuit-level technique using a triple feedback loop to optimize simultaneously gain, bandwidth and impedance matching without the penalty of added DC power dissipation. The circuit has been fabricated using a 130 nm silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The LNA has a peak gain of 9.3 dB, a minimum noise figure of 4.6 dB and an input compression point (IP1dB) higher than −9.9 dBm. It consumes only 5.4 mW using a single 1.5 V supply voltage, while working over a bandwidth from 14 to 58 GHz and occupying an area of $\mathbf{0.6}\times \mathbf{0.48}\ \mathbf{mm}^{2}$ including pads.

This paper presents design and characterization of a broadband low-noise amplifier (LNA) operating in the frequency range from 30 GHz to 110 GHz realized in a 0.35 μm SiGe:C bipolar technology. The circuit achieves a wide bandwidth by means of a T-type interstage matching network combined with an additional L-type admittance inverter. The LNA achieves a maximum measured gain of 18 dB. The measured noise figure is below 10.5 dB in the frequency range from 50 to 67 GHz. The circuit exhibits an output-referred 1 dB compression point of 0.5 dBm measured at 64 GHz. The LNA consumes 25 mA from a single 1.8 V supply. The active chip area is only 300 μm × 240 μm. The presented circuit is suitable for various ultra-wideband applications, such as e.g. backhaul communication systems, broadband on-chip vector network analyzer or millimeter-wave imaging.