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A novel fabrication technique for submicrometer trench isolation is proposed. This features a phosphorus-doped polysilicon field shield filled into the trench and a thick isolation oxide formed on polysilicon by impurity-enhanced oxidation (IEO). Due to the oxide entirely covering the trench shoulder by a self-aligned process, the proposed structure has notable merits: (i) the anomalous hump current in Id-Vg subthreshold characteristics is suppressed even in a narrow-channel transistor and (ii) the proposed structure provides less susceptibility to crystal defect generation. These can facilitate fabrication of controllable devices. In addition, a deeply implanted channel stopper yields a low parasitic capacitance for fast device operation and excellent isolation performance characteristics such as low field penetration and low punch-through current. These are attributed to the effect of the electric field shield.

A dual-frequency superimposed (DFS) 100 MHz and 3.2 MHz rf capacitive-coupled plasma etch process for sub-90 nm devices has been developed. The electron density of DFS reactive ion etching (RIE) plasma at 40 mTorr was controlled from 4.0×1010 to 3.6×1011 cm-3 by adjusting the 100 MHz rf power, and the self-bias voltage (-V dc) was controlled from 20 to 760 V by adjusting the superimposed 3.2 MHz rf power. DFS RIE demonstrated independent control of electron density and self-bias voltage in a wide range. In the damascene etch process of SiOC film using Si3N4 as an etch mask, it was found that mask edge erosion is dependent on ion energy regardless of the selectivity of SiOC to Si3N4. DFS RIE offers the most suitable process for damascene etching of SiOC, which requires precise ion energy control.