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In this work, we develop a model for forecasting the stock market using News Headlines. The main step of the work is to pre-process daily news, as well as Opinion Finding method to generate features for the prediction problem. The target variable is a binary variable which takes value of 1, when the Dow Jones Industrial Average (DJIA) increases, and zero otherwise. A deep learning model with Long Short-Term Memory (LSTM) architecture to improve the prediction of the changes in DJIA. As a baseline, a time series data of DJIA is used without daily news. Then, we develop a model of time series prediction along with N-Gram of daily news. We discuss how N-gram model can help to improve the baseline. In the main pre-processing task, we develop a sentiment analysis (using polarity lexicons). This model assigns weights as sentiment polarity to all the news headlines. We also find the scores for degree of subjectivity and objectivity in news headlines, and we use them as additional features in our model. In experiments, an LSTM model is developed. A grid search is used to find the best architecture along with the effect of generated features from text pre-processing and Opinion Finding on time series forecasting.

Despite the growing popularity of field-programmable gate arrays (FPGA), this technology still suffers from drawbacks such as larger area, higher power consumption and longer runtime than application-specific integrated circuits (ASIC). Reconfiguration capability gives FPGAs an advantage over ASIC and can make it a more appropriate option for implementing some applications. One important issue regarding the reconfiguration process is the time it takes to carry out this procedure. This paper seeks to accelerate the reconfiguration process by using a bitstream compression method with a primary focus on FPGA architecture. Since multiplexers are among the main components of FPGAs, the proposed method is focused on encoding and compression of configuration bitstream for such resources. In addition, the bitstream format and the decompression operation are designed to obtain desirable results in terms of area overhead and time improvement. Results of experiments show that in comparison to the basic scheme, the proposed design improves the reconfiguration time by 33%.

The size of configuration bitstreams of field-programmable gate arrays (FPGA) is increasing rapidly. Compression techniques are used to decrease the size of bitstreams. In this paper, an appropriate bitstream format and variable symbol lengths are proposed to utilize the routing patterns for enhancing the compression efficiency. An order of inputs of multiplexers in switch modules is also proposed to improve the symbol statistics and hence, the compression efficiency. A framework to generate the bitstream and hardware description of FPGAs is developed as well. Experimental results over 20 MCNC benchmarks show that by applying the proposed approaches, the compression rate is improved by 46% on average compared to the methods with fixed symbol lengths without any area and performance degradation.

One of the major challenges in the process of three-dimensional integrated circuit fabrication is the manufacturing of through silicon vias (TSV). These TSVs compared with other connection elements require high manufacturing costs as well as large silicon area. In this paper, replication technique has been used to reduce the number of TSVs in 3D FPGAs. Replication is implemented for circuit input pads and logic blocks. Experimental results over 20 MCNC benchmarks show 33% and 20% reduction in the number of TSVs and delay on average, respectively, at the cost of 3% more logic blocks and 3% more input pads that they place in the unused resources of FPGA.

SRAM-based FPGAs suffer from soft errors caused by cosmic particles. This paper introduces a new switch box architecture to mitigate soft errors. In this switch box architecture, the number of SRAM bits required for programming the switch boxes is reduced by means of switch reduction with slight impact on routing capability of the switch box. This architecture does not require any modification of the existing placement and routing algorithms. The proposed architecture was evaluated on several MCNC benchmarks using VPR tool. The experimental results show that this architecture decreases the susceptibility of switch boxes to single event upsets by about 18% on average compared to the traditional ones. Also, our architecture decreases the probability of ridging and short faults in the switch boxes by about 32% on average.

In recent years, parameter variations present critical challenges for manufacturability and yield on integrated circuits. In this paper, a new method for improving the timing yield of field programmable gate array (FPGA) devices affected by random and systematic within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations average critical path delay is reduced under conditions of large random and systematic variation considering spatial correlation. Compared to the previous approach which is limited to a fixed placement, our method improves timing yield by attempting several placements and routings without lengthy placement and routing phases to handle systematic variations and spatial correlation. The average critical path delay is reduced by 7% compared to the previous work over 20 MCNC benchmarks. General Terms: FPGA, process variation, placement, routing

3D technology is an attractive solution for reducing wirelength in a field programmable gate array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we propose a tilable switch module architecture based on the 3D disjoint switch module for 3D FPGAs. Experimental results over 20 MCNC benchmarks show 62% reduction in the number of TSVs on average and small improvements in horizontal channel width and delay compared to the original 3D disjoint SM.

Mammography is a low dose x-ray technique that's used to create an image of the breast. It is an efficient way for early detection of any cancerous changes and malignancy of lumps. Mammographic images are usually archived and in many cases are transferred on Internet. Therefore, compression of these images has attracted the attention of many researchers. In this paper an efficient method is proposed for lossless compression of mammographic images. Gradual compression of prediction errors in an iterative manner is the basic idea of the proposed method. The simulation results were compared with standard image compression routines such as JPEG-LS, JPEG2000, JBIG and PNG. The superiority of the proposed method was shown for compression of mammographic images.

Microarray image technology is a powerful tool for monitoring the expression of thousands of genes simultaneously. Each microarray experiment produces large amount of image data, hence efficient compression routines that exploit microarray image structures are required. In this paper we introduce a lossless image compression method which segments the pixels of the image into three categories of background, foreground, and spot edges. The segmentation is performed by finding a threshold value which minimizes the weighted sum of the standard deviations of the foreground and background pixels. Each segment of the image is compressed using a separate predictor. The results of the implementation of the method show its superiority compared to the well-known microarray compression schemes as well as to the general lossless image compression standards.