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Among other new device concepts, nickel silicide (NiSix)-based Schottky barrier nanowire transistors are projected to supplement down-scaling of the complementary metal-oxide-semiconductor (CMOS) technology as its physical limits are reached. Control over the NiSix phase and its intrusions into the nanowire are essential for superior performance and down-scaling of these devices. Several works have shown control over the phase, but control over the intrusion lengths has remained a challenge. To overcome this, we report a novel millisecond-range flash-lamp-annealing (FLA)-based silicidation process. Nanowires are fabricated on silicon-on-insulator substrates using a top-down approach. Subsequently, Ni silicidation experiments are carried out using FLA. It is demonstrated that this silicidation process gives unprecedented control over the silicide intrusions. Scanning electron microscopy and high-resolution transmission electron microscopy are performed for structural characterization of the silicide. FLA temperatures are estimated with the help of simulations.

Here, we report the observation of negative photoconductance (NPC) effect in highly arsenic-doped germanium nanowires (Ge NWs) for the infrared light. NPC was studied by light-assisted Kelvin probe force microscopy, which shows the depletion of carriers in n-Ge NWs in the presence of infrared light. The trapping of photocarriers leads to high recombination of carriers in the presence of light, which is dominant in the n-type devices. Furthermore, a carrier trapping model was used to investigate the trapping and detrapping phenomena and it was observed that the NPC in n-Ge occurred, because of the fast trapping of mobile charge carriers by interfacial states. The performance of n-type devices was compared with p-type NW detectors, which shows the conventional positive photoconductive behavior with high gain of 104. The observed results can be used to study the application of Ge NWs for various optoelectronic applications involving light tunable memory device applications.

The fabrication of p-type silicon junctionless tri-gate transistors and their temperature dependent transport studies are reported in this work. The fabricated transistors have shown a good transfer characteristic down to a low temperature of ~ 80 K with an ON/OFF ratio of 106. The threshold voltage and the subthreshold slope were found to be dependent on temperature. In particular, the threshold voltage and the flat band voltage have positive slopes of 2.24 and 1.19 mV K−1, respectively, with temperature. Channel resistance was found to be increasing with decreasing temperature. The devices have shown a typical 1/f noise behavior in the frequency range of (1–50) Hz and 1/f2 type behavior in the frequency range of (50–100 Hz). At a temperature of 4.2 K, current vs. gate voltage characteristic at a fixed source drain bias shows clear coulomb peaks with different intervals for different gate bias voltages and the observed spikes were consistent within the sub-bands. We relate this to the single hole tunneling, mediated by the charged acceptors available in the channel region. Coupling strength of the dopants was also studied.

Introduction: For decades the miniaturization of logic circuitry was a result of down scaling of the field effect transistor (FET). This scaling has reached its end and, therefore, new device materials and concepts have been under research for the last years. One approach is to increase the functionality of an individual device rather than scaling down its size. Such a device concept is the reconfigurable FET (RFET), which can be configured to n- or p-polarity dynamically [1]. RFETs are based on Schottky barrier FETs and feature an intrinsic Si nanowire (NW) channel. The Schottky junctions are formed by placing Nickel (Ni) contacts on both ends of the NW and conductive Ni-silicide segments are formed in the NW by an annealing process. In RFETs, two gates are usually placed on top of these Schottky junctions and by the application of electrostatic potential at the gates unipolar n- or p-transport is tuned in the channel. There are several Ni-silicide phases out of which NiSi2 is preferred as it yields sharp NiSi2-Si junctions. Moreover, its metal work function is near the mid bandgap of Si. This enables tuning the RFET to n- or p-transport by respectively bending the bands when applying electrostatic potential at the gates (Fig. 1). Top-down fabrication of Schottky barrier FETs is a pre-requisite for the large-scale integration of RFETs. The challenges in this fabrication process include proper patterning of NWs, obtaining symmetric p- and n-currents and the scalability of the devices. The first two tasks have been solved as reported in [2]. However, the lack of controllable intrusion of silicide into the NWs remains an obstacle for device scalability [3-5]. Here we report that a silicidation process based on millisecond flash lamp annealing (FLA) significantly improves the uniformity of silicide intrusion at the two ends of the NWs. Such a gain in silicidation control will decisively allow creating RFETs with short channel lengths. Fabrication: The devices are fabricated on silicon-on-insulator (SOI) substrates with 20 nm undoped top Si layer and 102 nm buried oxide. Electron beam lithography (EBL) and dry etching are used to fabricate NWs with 20 nm width as described in [3]. NWs are oxidized with a rapid thermal process and a ~6 nm thick SiO2 shell is formed to passivate NW surface. After wet etching SiO2 from desired areas, Ni contacts are placed in those areas using EBL and Ni evaporation. FLA is used for silicidation of the NWs and the results show equally long silicide intrusions (Fig. 2). Results: The FLA process time is much shorter (0.5-20 ms) compared to conventional rapid thermal annealing (RTA) [6]. FLA based silicidation process is developed which, unlike previously reported RTA based processes, can deliver scalable RFETs. High resolution TEM (HRTEM) shows the formation of the desired NiSi2 phase and atomically abrupt Schottky junctions (Fig. 4). This is also confirmed by element mapping based on energy dispersive X-ray spectroscopy (EDXS) (Fig. 3). The transfer characteristics of the device with back-gate operation show an ambipolar behavior with an ON/OFF ratio of 9 orders of magnitude (Fig. 5). The gate voltage (VBG) was swept from -30 V to 30 V and the drain to source voltage (VD) was varied from 0.25 V to 0.75 V. The unipolar behavior can be tuned by fabricating two or more top gates. This will also reduce the additional hysteresis caused by using the buried oxide as a very thick gate dielectric. Applications: The FLA-based silicidation process enables channel scaling. Devices based on this process show promising results and have potential applications as devices with reduced power consumption and low chip area [7]. These RFETs can also be used for the fabrication of power-efficient multi-independent gate-based logic circuits [8]. Moreover, the number of transistors and the chip area consumption can be reduced with the help of these transistors, preserving at the same time the functionality of the integrated circuits [9]. 1.Heinzig, A. et al., Nano Lett., 2011.12(1):pp.119-124. 2.Simon, M. et al.,IEEE Trans Nanotechnol, 2017.16(5):pp.812-819. 3.Khan, B.M. et al., Appl. Sci. 2019. 9(17),3462. 4.Habicht, S. et al., Nanotechnology, 2010. 21(10): pp.105701. 5.Ogata, K. et al., Nanotechnology,2011.22(36):pp.365305. 6.Rebohle, L. et al., Semicond Sci Technol, 2016. 31(10): pp.103001. 7.Gaillardon, P.E. at al., in LATS, 2016, pp.195-200. 8.Rai, S. et al., IEEE Transactions VLSI, 2019.27(3):pp.560-572. 9.Raitza, M., et al., in DATE.2017,pp.338-343.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

This article presents a review of various methods for extracting the key parameters of junctionless (JL) MOSFETs, namely, the threshold voltage, flat-band voltage, doping concentration, carrier mobility, and parasitic series resistance. The applicability and limitations of different methods are analyzed using numerical simulations and experimental data for planar and tri-gate nanowire JL transistors with various nanowire widths.

Introduction: Reconfigurable field effect transistors (RFET) have the ability to toggle polarity between n- and pconductance at runtime [1], [2]. The here presented multiple independent gate (MIG) RFET expands the device functionality by offering additional logical inputs, valuable for e.g. efficient XOR or majority gate implementations [3], [4] or the here originally presented multiplexer circuit. Moreover, for the first time with a top-down RFET approach equal ON-currents are obtained for every configuration while requiring only one supply voltage (VDD). Working principle: The presented RFET consists of an intrinsic silicon nanowire channel (Fig. 1a). At both ends NiSi₂ is intruded, which has a work function aligned near to the middle of the Si band gap. Each of the resulting Schottky junctions is gated individually (CG1, PG) and additional gates are introduced along the channel (CG2, CG3). The program gate (PG) determines the device’s polarity and has the same potential as the corresponding drain (0 V for hole or VDD for electron conductance). If all control gates (CG1-3) are biased equally, the RFET turns ON Fig. 3a, b, f, g). Whenever any or all CGs are biased equally to the source’s potential, a potential barrier is formed, switching the RFET OFF (Fig. 3c-e, h-j). Hence, the FET works as wired-AND logic gate (Fig. 6a). The fabrication with CMOS compatible processes and materials is based on a 20 nm silicon-on-insulator (SOI) wafer and requires no doping. The nanowire is formed by a reactive ion etch process [5]. By repeated oxidation and HF etching the wire is further rounded and thinned to ca. 60 nm width and 4 nm height. An omega-shaped gate stack of 5 nm SiO₂, and conductive TiN, Ti and Pt surrounds and radially compresses the wire (Fig. 1b). Finally, nickel is deposited at both ends of the wire and atomically abrupt and flat NiSi₂ Schottky junctions are formed (Fig. 1c). Performance: The transfer characteristics in Fig. 4 reveal an ON/OFF ratio of five orders of magnitudes and ONcurrents which are equal regardless of the programmed configuration. Additionally, only one supply voltage is needed for gates and drain. Despite its necessity for the use in complementary logic circuits, this symmetry was never achieved before for top-down fabricated RFETs. For NiSi₂ and Si, the Schottky barrier height is slightly lower for holes than for electrons leading to initially asymmetric ON-currents. However, by the influence of the omega gate stressor on the band structure the electron and hole injection through the Schottky barrier can be equalized as demonstrated in Fig. 2 [6]. Fig. 4 further shows that the minimum subthreshold swing SS and threshold voltage are lower for the switching with CG2 and CG3 than for all combinations including CG1. This is because CG1 directly controls the inlet at the Schottky junction whereas the other gates only build a conventional channel barrier. Having two efficiently switching gates (CG2+3), as demonstrated for the first time, thus improves the efficiency of RFETs. From Fig. 5 it can be seen that the gates’ voltage determines the shape of the output characteristics. Hole dominated currents rise with retard because the injecting Schottky barrier is still non-transparent for tunneling at VD = 0 V. Applications of the device reach from camouflage circuits for hardware secure authentication [7] and fine-grained FPGAs [8] over area and power-delay optimized circuits [3], [4] to novel logic synthesis based on majority-inverter graphs [9]. As a graspable and novel example, the presented device can serve as transmission gate (Fig. 6b) in a multiplexer (MUX) (Fig. 6c, d), which requires program gates at both in- and output. An n-bit MUX can be reduced by every second stage, thus only (2^[n+1]− 2^i)/3 transmission gates are required, with i=1 for odd and i=2 for even numbers of n (with classical CMOS: 2^[n+1] − 2). For a 4-bit MUX this results in altogether 30% less transistors when considering also the select and program signal inverters and the reduced buffer needs (Fig. 6e). Eventually, more gates per transistor can further reduce the transistor count, e.g. for a 5-gate RFET in a 6-bit MUX by even 42%. [1] A. Heinzig et al., Nano Lett., vol. 12, no. 1, pp. 119–124, (2012). [2] M. D. Marchi et al., in Electron Devices Meeting (IEDM), 2012 IEEE International, pp. 8.4.1–8.4.4, (2012). [3] P.-E. Gaillardon et al., in Test Symposium (LATS), 2016 17th Latin-American, pp. 195–200, (2016). [4] J. Trommer et al., in 2016 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 169–174, (2016). [5] M. Simon et al., IEEE Trans. Nanotechnol., vol. 16, no. 5, pp. 812–819, (2017). [6] T. Baldauf et al., Solid-State Electron., vol. 128, pp. 148–154, (2017). [7] Y. Bi et al., in 2014 IEEE 23rd Asian Test Symposium, pp. 342–347, (2014). [8] P. E. Gaillardon et al., IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 10, pp. 2187–2197, (2015). [9] L. Amaru et al., Proc. IEEE, vol. 103, no. 11, pp. 2168–2195, (2015).

Films of self assembled diblock copolymers (BCPs) have attracted significant attention for generating semiconductor nanoarrays of sizes below 100 nm through a simple low cost approach for device fabrication. A challenging abstract is controlling microdomain orientation and ordering dictated by complex interplay of surface energies, polymer–solvent interactions and domain spacing. In context, microphase separated poly (styrene-b-ethylene oxide) (PS-b-PEO) thin films is illustrated to fabricate nanopatterns on silicon and germanium materials trenches. The trenched templates was produced by simple electron beam lithography using hydrogen silsesquioxane (HSQ) resist. The orientation of PEO, minority cylinder forming block, was controlled by controlling trench width and varying solvent annealing parameters viz. temperature, time etc. A noticeable difference in microdomain orientation was observed for Si and Ge trenches processed under same conditions. The Ge trenches promoted horizontal orientations compared to Si due to difference in surface properties without any prior surface treatments. This methodology allows to create Ge nanopatterns for device fabrication since native oxides on Ge often induce patterning challenges. Subsequently, a selective metal inclusion method was used to form hardmask nanoarrays to pattern transfer into those substrates through dry etching. The hardmask allows to create good fidelity, low line edge roughness (LER) materials nanopatterns.

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10(20) atoms cm(-3). Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.

To maintain semiconductor device scaling, in recent years industry has been forced to move from planar to non-planar device architectures. This alone has created the need to develop a radically new, non-destructive method for doping. Doping alters the electrical properties of a semiconductor, related to the access resistance. Low access resistance is necessary for high performance technology and reduced power consumption. In this work the authors reduced access resistance in top–down patterned Ge nanowires and Ge substrates by a non-destructive dopant in-diffusion process. Furthermore, an innovative electrical characterisation methodology is developed for nanowire and fin-based test structures to extract important parameters that are related to access resistance such as nanowire resistivity, sheet resistance, and active doping levels. Phosphine or arsine was flowed in a Metalorganic Vapour Phase Epitaxy reactor over heated Ge samples in the range of 650–700 °C. Dopants were incorporated and activated in this single step. No Ge growth accompanied this process. Active doping levels were determined by electrochemical capacitance–voltage free carrier profiling to be in the range of 1019 cm−3. The nanowires were patterned in an array of widths from 20–1000 nm. Cross-sectional Transmission Electron Microscopy of the doped nanowires showed minimal crystal damage. Electrical characterisation of the Ge nanowires was performed to contrast doping activation in thin-body structures with that in bulk substrates. Despite the high As dose incorporation on unpatterned samples, the nanowire analysis determined that the P-based process was the better choice for scaled features.

Display Omitted Study of a new electron beam resist, SML.Contrast is as high as PMMA.Dense grating with linewidth from ~5 to 8nm demonstrated in SML and ZEP.Etch resistance equivalent to ZEP resist. We present study on a novel, positive-tone electron beam lithography (EBL) resist known as SLM and compare its lithographic performance to well-established positive resists such as 950K polymethyl methacrylate (PMMA) and ZEP 520A. SML has been fabricated to have processing parameters similar to PMMA, but with enhanced functionality. Processing parameters such as film deposition, baking temperatures as well as the developers used for PMMA work well with SML resist.Contrast curve measurements were generated for different thicknesses of SLM and exposure voltages. Two temperature variants were employed for developing the resist with 7:3 IPA:water co-solvent developer, viz. room temperature and 0?C. To verify the resolution of SML resist, dense gratings of single pixel lines were compared to those fabricated using 950K PMMA and ZEP 520A resists. Fundamental pattern transfer skills of metal lift-off and dry etching were compared with ZEP. Metal lift-off was carried out using 5-10nm thick chromium metal and Microposit 1165 resist remover. The resilience of the SML resist to dry etching (ICP etching system with SF6 and C4F8 gas mixture) was compared to ZEP and PMMA resists and then dense gratings on ZEP and SML were etched into Si.The data obtained from the contrast curves show high contrast of the new resist. From the grating results, SML demonstrates very high resolution like ZEP and PMMA. The pattern transfer abilities of SML are also similar and in some aspects even outdo that of ZEP resist.

From Springer description: "We present the design considerations of an autonomous wireless sensor and discuss the fabrication and testing of the various components including the energy harvester, the active sensing devices and the power management and sensor interface circuits. A common materials platform, namely, nanowires, enables us to fabricate state-of-the-art components at reduced volume and show chemical sensing within the available energy budget. We demonstrate a photovoltaic mini-module made of silicon nanowire solar cells, each of 0.5 mm2 area, which delivers a power of 260 μW and an open circuit voltage of 2 V at one sun illumination. Using nanowire platforms two sensing applications are presented. Combining functionalised suspended Si nanowires with a novel microfluidic fluid delivery system, fully integrated microfluidic–sensor devices are examined as sensors for streptavidin and pH, whereas, using a microchip modified with Pd nanowires provides a power efficient and fast early hydrogen gas detection method. Finally, an ultra-low power, efficient solar energy harvesting and sensing microsystem augmented with a 6 mAh rechargeable battery allows for less than 20 μW power consumption and 425 h sensor operation even without energy harvesting."

Ge-on-Si and Ge-on-insulator (GeOI) are the most promising materials for the next-generation nanoelectronics that can be fully integrated with silicon technology. To this day, the fabrication of Ge-based transistors with a n-type channel doping above 5 × 1019 cm−3 remains challenging. Here, we report on n-type doping of Ge beyond the equilibrium solubility limit (ne ≈ 6 × 1020 cm−3) together with a nanoscale technique to inspect the dopant distribution in n++-p junctions in GeOI. The n++ layer in Ge is realized by P+ ion implantation followed by millisecond-flashlamp annealing. The electron concentration is found to be three times higher than the equilibrium solid solubility limit of P in Ge determined at 800 °C. The millisecond-flashlamp annealing process is used for the electrical activation of the implanted P dopant and to fully suppress its diffusion. The study of the P activation and distribution in implanted GeOI relies on the combination of Raman spectroscopy, conductive atomic force microscopy, and secondary ion mass spectrometry. The linear dependence between the Fano asymmetry parameter q and the active carrier concentration makes Raman spectroscopy a powerful tool to study the electrical properties of semiconductors. We also demonstrate the high electrical activation efficiency together with the formation of ohmic contacts through Ni germanidation via a single-step flashlamp annealing process.Ge-on-Si and Ge-on-insulator (GeOI) are the most promising materials for the next-generation nanoelectronics that can be fully integrated with silicon technology. To this day, the fabrication of Ge-based transistors with a n-type channel doping above 5 × 1019 cm−3 remains challenging. Here, we report on n-type doping of Ge beyond the equilibrium solubility limit (ne ≈ 6 × 1020 cm−3) together with a nanoscale technique to inspect the dopant distribution in n++-p junctions in GeOI. The n++ layer in Ge is realized by P+ ion implantation followed by millisecond-flashlamp annealing. The electron concentration is found to be three times higher than the equilibrium solid solubility limit of P in Ge determined at 800 °C. The millisecond-flashlamp annealing process is used for the electrical activation of the implanted P dopant and to fully suppress its diffusion. The study of the P activation and distribution in implanted GeOI relies on the combination of Raman spectroscopy, conductive atomic force microscopy, an...

The junctionless nanowire metal–oxide–semiconductor field-effect transistor (JNT) has recently been proposed as an alternative device for sub-20-nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS-compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an ION/IOFF current ratio of 1.2 × 103 at VD = –1 V and drain-induced-barrier lowering (DIBL) of 87 mV. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

A method for cross-sectional doping of individual Si/SiO2 core/shell nanowires (NWs) is presented. P and B atoms are laterally implanted at different depths in the Si core. The healing of the implantation-related damage together with the electrical activation of the dopants takes place via solid phase epitaxy driven by millisecond-range flash lamp annealing. Electrical measurements through a bevel formed along the NW enabled us to demonstrate the concurrent formation of n- and p-type regions in individual Si/SiO2 core/shell NWs. These results might pave the way for ion beam doping of nanostructured semiconductors produced by using either top-down or bottom-up approaches.

Hyperdoping consists of the intentional introduction of deep-level dopants into a semiconductor in excess of equilibrium concentrations. This causes a broadening of dopant energy levels into an intermediate band between the valence and conduction bands.[1,2] Recently, bulk Si hyperdoped with chalcogens or transition metals has been demonstrated to be an appropriate intermediate-band material for Si-based short-wavelength infrared photodetectors.[3-5] Intermediate-band nanowires could potentially be used instead of bulk materials to overcome the Shockley-Queisser limit and to improve efficiency in solar cells,[6-9] but fundamental scientific questions in hyperdoping Si nanowires require experimental verification. The development of a method for obtaining controlled hyperdoping levels at the nanoscale concomitant with the electrical activation of dopants is, therefore, vital to understanding these issues. Here, we show a CMOS-compatible technique based on non-equilibrium processing for the controlled doping of Si at the nanoscale with dopant concentrations several orders of magnitude greater than the equilibrium solid solubility. Through the nanoscale spatially controlled implantation of dopants, and a bottom-up template-assisted solid phase recrystallization of the nanowires with the use of millisecond-flash lamp annealing, we form Se-hyperdoped Si/SiO2 core/shell nanowires that have a room-temperature sub-band gap optoelectronic photoresponse when configured as a photoconductor device.

The surface roughness of hydrogen silsesquioxane (HSQ) as a negative tone electron beam (EB) resist has been studied as a function of exposure dose, developer concentration, and pre-exposure bake temperature. In the range of low exposure doses, the surface roughness of HSQ drops rapidly with an increase in the dose. It levels off at about 1 nm around the dose at which the respective contrast curve saturates. The TMAH developer concentration, varied in the range of 2.5–25%, has only a slight influence on the HSQ roughness. The increase of the baking temperature from 90 to 220 °C, however, causes a significant rise in the roughness of more than 100%. These results are discussed in terms of structural changes and network formation in thin HSQ films. They prove that a process combining high developer concentration and low baking temperature is preferable for fabrication of high resolution patterns using HSQ as a negative tone EB resist.

A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This ki ...

3D vertically stacked silicon nanowire (SiNW) field effect transistors (FET) with high density arrays (up to 7×20) of fully depleted and ultra-thin (15–30 nm) suspended channels were fabricated by a top-down CMOS compatible process on silicon on insulator (SOI). The channels can be wrapped by conformal high-κ gate dielectrics (HfO 2 ) and their conductivity can be excellently controlled either by a reference electrode or by three local gates; a backgate (BG) and two symmetrical Pt side-gates (SG) offering unique sensitivity tuning. Such 3D structure has been (3-Aminopropyl)-triethoxysilane (APTES) functionalized and biotynilated for pH and streptavidin (protein) sensing, respectively. An ultra-low concentration of 17 aM of streptavidin was measured, the lowest ever reported in literature. Extremely high quasi-exponential drain current responses (ΔI d /pH) of ∼0.70 dec/pH were measured for structures with APTES functionalized SiO 2 gate dielectrics when operated in the subthreshold regime. Also, high drain current responses > 20 µA/pH and high sensitivities (S ∼ 95%) were measured for structures with a native oxide gate dielectrics when operated in the strong-inversion regime.

In this chapter, we introduce two specific types of junctionless nanowire transistors (JNTs): (i) silicon-on-insulator (SOI) back-gated JNTs for sensing applications and (ii) germanium-on-insulator (GeOI) top-gated JNTs for digital logic applications. We discuss in detail the suitability of junctionless architecture for these particular applications and present results on device fabrication and characterisation. Back-gated JNTs of 45 different channel geometries (different numbers, lengths, and widths of channel nanowires) have been designed and fabricated with very high precision (down to 10 nm widths of the nanowires) on SOI wafers using a fully CMOS-compatible fabrication process. Electrical characterisation of the fabricated devices has demonstrated their excellent performance as back-gated JNTs. Furthermore, data from pH and streptavidin sensing experiments have proven their good sensing properties. These JNTs are among the smallest top-down fabricated nanowire sensing devices reported to date. Top-gated JNTs with Ge nanowire channels of widths down to 20 nm have been fabricated by a simple CMOS-compatible process on GeOI wafers with a highly p-doped (~1×1019 cm−3) top germanium layer. The fabricated devices have demonstrated decent output and transfer characteristics with relatively high I on /I off current ratios of up to 2.0 × 105 and steep subthreshold slopes of 189 mV/dec. To the best of our knowledge, these are the first reported Ge JNTs.

A micro-power energy harvesting system based on core(crystalline Si)-shell(amorphous Si) nanowire solar cells together with a nanowire-modified CMOS sensing platform have been developed to be used in a dust-sized autonomous chemical sensor node. The mote (SiNAPS) is augmented by low-power electronics for power management and sensor interfacing, on a chip area of 0.25mm(2). Direct charging of the target battery (e. g., NiMH microbattery) is achieved with end-to-end efficiencies up to 90% at AM1.5 illumination and 80% under 100 times reduced intensity. This requires matching the voltages of the photovoltaic module and the battery circumventing maximum power point tracking. Single solar cells show efficiencies up to 10% under AM1.5 illumination and open circuit voltages, Voc, of 450-500mV. To match the battery's voltage the miniaturised solar cells (similar to 1mm(2) area) are connected in series via wire bonding. The chemical sensor platform (mm 2 area) is set up to detect hydrogen gas concentration in the low ppm range and over a broad temperature range using a low power sensing interface circuit. Using Telran TZ1053 radio to send one sample measurement of both temperature and H-2 concentration every 15 seconds, the average and active power consumption for the SiNAPS mote are less than 350nW and 2.1 mu W respectively. Low-power miniaturised chemical sensors of liquid analytes through microfluidic delivery to silicon nanowires are also presented. These components demonstrate the potential of further miniaturization and application of sensor nodes beyond the typical physical sensors, and are enabled by the nanowire materials platform.

A high-gain photodetector based on junctionless MOSEFT has been presented in this work. Tri-gate junctionless nanowire phototransistors were fabricated on (100) silicon-on-insulator wafers with a buried oxide of thickness 145 nm and top silicon layer of thickness 10 nm. The gate stack consisted of a 10 nm SiO2 dielectric and a 50 nm poly-Si gate electrode. The channel length and doping concentration of junctionless n-MOSFETs was 1 μm and 3 × 1019 cm−3, respectively. The dark current of this device measured at room temperature was less than 1 pA. The measured internal gain of the device was about 35 for 860 nm light illumination. The photocurrent was 300 times larger than the dark current for only 30 nW incident power on the nanowire at 300 mV drain bias.

The authors report a chemical process to remove the native oxide on Ge and Bi2Se3 crystals, thus facilitating high-resolution electron beam lithography (EBL) on their surfaces using a hydrogen silsesquioxane (HSQ) resist. HSQ offers the highest resolution of all the commercially available EBL resists. However, aqueous HSQ developers such as NaOH and tetramethylammonium hydroxide have thus far prevented the fabrication of high-resolution structures via the direct application of HSQ to Ge and Bi2Se3, due to the solubility of components of their respective native oxides in these strong aqueous bases. Here we provide a route to the generation of ordered, high-resolution, high-density Ge and Bi2Se3 nanostructures with potential applications in microelectronics, thermoelectric, and photonics devices.

Study of topographical and structural changes occurring in a positive resist known as SML after electron beam lithography are presented in this article. The authors also defined its chemical structure, which is very important for understanding the lithographic performance of the resist. The structural and lithographic properties of SML have been compared to the traditional ZEP resist. First, the change in the surface roughness with respect to the electron dose of SML and ZEP resists was measured. It was found that both resists start off with similar initial roughness values. However, ZEP was observed to have a higher roughness at the apex electron dose, thereafter a reduction in roughness was observed. The roughness variation in the two resists reflected on the resolution of the gratings that were patterned in both the resists. Gratings in SML showed smoother line edge roughness, and the patterns transferred using SML resist showed more even features than the ones transferred with ZEP. Subsequently, to understand the chemical composition of the new resist, Fourier transform infrared spectroscopy (FTIR) measurements were performed on both the resists as well as on poly(methyl methacrylate) (PMMA) and their spectra were compared. The FTIR spectra revealed that SML had a chemical structure similar to ZEP and PMMA polymers. The high sensitivity of ZEP is attributed to the Cl group in the compound, which is not present in SML and PMMA and can therefore explain their lower sensitivity to electron exposure in comparison to ZEP. Unlike PMMA but comparable to ZEP, SML shows an IR peak at a wavenumber close to 850 cm−1, suggesting the presence of α-methylstyrene group within its chemical structure, which accounts for the resist's high etch durability, similar to ZEP. Additional FTIR measurements of pre- and postexposed resists together with their attributions to the resolution of the SML and ZEP resists is also demonstrated in this article. The data presented in the study highlights the chemical properties of SML and ZEP resists polymers and correlates them to their lithographic performance.

A high precision alignment concept is evaluated for suitability in UV-based nanoimprint lithography. Through three consecutive alignment steps an overlay accuracy of 50nm is obtained with ample room for further improvements.

Electrically variable shallow junction metal–oxide–semiconductor field effect transistors on silicon on insulator have been fabricated to evaluate the suitability of fabrication processes on a nanoscale. In addition, the limits of scalability have been explored reducing gate lengths down to 12 nm. Specific attention has been paid to the overlay accuracy as required for the fabrication of these double gate structures. The superior quality of hydrogen silsesquioxane (HSQ) as electron beam resist and as mask material is demonstrated. The transistor fabricated exhibits extremely low leakage currents and relatively high on currents. The 8 orders of magnitude difference between the on and off states demonstrates conclusively large potentials for metal–oxide–semiconductor structures with critical dimensions in the 10 nm regime.

Silicon nanowire (SiNW) field effect transistors (FETs) have been widely investigated as biological sensors for their remarkable sensitivity due to their large surface to volume ratio (S/V) and high selectivity towards a myriad of analytes through functionalization. In this work, we propose a long channel (L > 500 nm) junctionless nanowire transistor (JNT) SiNW sensor based on a highly doped, ultrathin body field-effect transistor with an organic gate dielectric epsilon(r) = 1.7. The operation regime (threshold voltage V-th) and electrical characteristics of JNTs can be directly tuned by the careful design of the NW/Fin FET. JNTs are investigated through 3D Technology Computer Aided Design (TCAD) simulations performed as a function of geometrical dimensions and channel doping concentration N-d for a p-type tri-gated structure. Two different materials, namely, an oxide and an organic monolayer, with varying dielectric constants er provide surface passivation. Mildly doped N-d = 1 x 10(19) cm(-3), thin bodied structures (fin width F-w < 20 nm) with an organic dielectric (epsilon(r) = 1.7) were found to have promising electrical characteristics for FET sensor structures such as V-th similar to 0 V, high relative sensitivities in the subthreshold regime S > 95%, high transconductance values at threshold g(m),(Vfg=0V) > 10 nS, low subthreshold slopes SS similar to 60 mV/dec, high saturation currents I-d,I-max similar to 1-10 mu A and high I-on/I-off > 10(4)-10(10) ratios. Our results provide useful guidelines for the design of junctionless FET nanowire sensors that can be integrated into miniaturized, low power biosensing systems. (c) 2013 Elsevier B.V. All rights reserved.

Silicon nanowire (Si NW) sensors have attracted great attention due to their ability to provide fast, low-cost, label-free, real-time detection of chemical and biological species. Usually configured as field effect transistors (FETs), they have already demonstrated remarkable sensitivity with high selectivity (through appropriate functionalisation) towards a large number of analytes in both liquid and gas phases. Despite these excellent results, Si NW FET sensors have not yet been successfully employed to detect single molecules of either a chemical or biological target species. Here we show that sensors based on silicon junctionless nanowire transistors (JNTs), the simplest possible transistors, are capable of detecting the protein streptavidin at a concentration as low as 580 zM closely approaching the single molecule level. This ultrahigh detection sensitivity is due to the intrinsic advantages of junctionless devices over conventional FETs. Apart from their superior functionality, JNTs are much easier to fabricate by standard microelectronic processes than transistors containing p–n junctions. The ability of JNT sensors to detect ultra-low concentrations (in the zeptomolar range) of target species, and their potential for low-cost mass production, will permit their deployment in numerous environments, including life sciences, biotechnology, medicine, pharmacology, product safety, environmental monitoring and security.