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To assess the clinical and imaging features of IgG4-RKD for understanding and diagnosis of this disease. CT and MR images of 34 patients with IgG4-RKD were retrospectively analyzed by two radiologists in consensus. The serum IgG4 level was found being increased in all patients. Renal involvement was bilateral (24/34, 70.6%) or unilateral (10/34,29.4%), multiple (29/34, 85.3%) or solitary (5/34, 14.7%). The lesions were wedge-shaped (21) or mass-like (4) in the renal parenchyma, whereas diffusely decreased renal density was noted in 2 patients. All lesions showed progressive contrast enhancement. The 4 mass-like lesions were misdiagnosed as renal malignancy. In 15 patients with follow-up imaging examinations, the number and size of renal lesions decreased after oral hormone treatment. The serum IgG4 levels were significantly decreased after therapy in all patients. IgG4-RKD has various imaging appearances. Although the mass-like appearance mimics renal malignancy in some patients, progressive contrast enhancement in the lesion with elevated serum IgG4 suggests IgG4-RKD.

This paper presents an automatic temperature correction design for carry chain based time-to-digital converter (TDC) in field-programmable gate array (FPGA). The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain. Accordingly, a simplified temperature correction scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this correction approach, a TDC precision of 21 ps has been achieved in Cyclone II FPGA under a wide ambient temperature range from 0 $^\circ{\rm C}$ to 60 $^\circ{\rm C}$ . Several design key points are also described in this paper.

The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper.

Aiming to high sensitivity and wide spectrum of cosmic ray detection, the Large High Altitude Air Shower Observatory (LHAASO) project consists of over 10,000 detectors of different types, spreading over 1.2 km2. To precisely reconstruct the air shower events with high angular resolution, all detector electronics and digitizers should work in synchronous acquisition mode with a global timing error less than 5 ns (rms). This large scale and high precision timing requirement exceeds the capability or feasibility of traditional methods such as GPS and echo-delay calibration. Recently an emerging method named White Rabbit (WR) was proposed and demonstrated as a cost-effective solution that combines Gigabit Ethernet data transfer and subnanosecond precision timing transfer over the same fiber media. Furthermore, the White Rabbit network also enables direct digitization and trigger-less data acquisition mode for each detector, which will greatly reduce the complexity and improve the performance of the data acquisition (DAQ) system. In this paper we will demonstrate the design and development status of a WR timing and DAQ network in the LHAASO project.

ZYNQ is the new all programmable SoC architecture of FPGA with dual-core high performance ARM Cortex-A9 processors from Xilinx. A new module with Giga-bit Ethernet interface based on the ZYNQ XC7Z010 is development for the High Purity Germanium Detectors' data acquisition in the CJPL (China JingPing under-ground Lab) experiment. With the new architecture of ZYNQ, the embedded open source Linux with TCP/IP stack and the real time high throughput logic based on VHDL can be combined to run in a single ARM + FPGA chip with lower profile, lower power and highest performance. It's very differently from the classic architecture with two chips, one processor plus one FPGA. This paper will introduce how about the architecture of the readout module and how the new module can archive higher performance than the classic one. Also the throughput of the Giga-bit Ethernet which more than 500Mbps will be introduce and a verify platform of HPGe data acquisition system based on the new module will also be introduced.

This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the similar temperature-LUT coefficient. Accordingly, a simplified temperature compensation scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this compensation approach, a 21ps RMS TDC resolution has been achieved in Cyclone II FPGA under a wide temperature range from 10°C to 75°C. Several design key points are also described in this paper.

Sub-nanosecond precision timing distribution and control are key techniques in various distributed real-time applications, where the proposed White Rabbit (WR) project provides a solution combining both data transmission and timing control via the same media. This paper demonstrates the design and development of a compact, standalone WR node following FPGA Mezzanine Card (FMC) standard, which would work as a common WR interface to different applications. Test results show that the timestamp synchronization precision of 65ps (RMS) has been observed between the node and a WR switch, and the data throughput of over 0.3Gbps has been verified in a preliminary test between the node and a PC host.