1. A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection
- Author
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Shirui Zhao, Wei Mao, Fengwei An, Hao Yu, and Haoran Lyu
- Subjects
business.industry ,Computer science ,Pipeline (computing) ,Deep learning ,Binary number ,Parallel processing (DSP implementation) ,Hardware and Architecture ,Memory architecture ,Path (graph theory) ,Artificial intelligence ,Electrical and Electronic Engineering ,Latency (engineering) ,Field-programmable gate array ,business ,Software ,Computer hardware - Abstract
Road detection is widely used in driving assistance and automotive driving. However, many state-of-the-art road de-tection methods are time-consuming and memory-consuming. In this paper, we propose an FPGA-based deep learning accelerator using the binary SegNet (BSegNet) with computing-near-memory (CNM) architecture for road detection at edges. The accelerator has optimized CNM architecture with massive bit-level parallel processing elements (PEs) and pipeline for low latency of the crit-ical path. The training model size of BSegNet with binary param-eters is only 2.1MB, and the BSegNet can achieve training accu-racy over 85% on KITTI and Cityscapes datasets. The RTL-level realized FPGA-accelerator can process the road detection with an energy-efficiency of 351.7 GOPs/W and only 18.70 W on-chip power.
- Published
- 2022