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We report on an early-time inverse gain comparison between ion and neutron irradiated silicon bipolar junction transistors. We find ion irradiations to be an excellent simulator for fast-burst neutrons for early-time behavior and damage creation rates. In addition we report on an experimental to simulation comparison of transient gain annealing response. The simulations are from a physics based modeling approach that is being developed at Sandia National Laboratories as part of the Qualification Alternatives to the Sandia Pulsed Reactor (QASPR) Program. We find excellent agreement between simulation and experiment across a wide range of irradiation conditions. Index Terms--Damage equivalence, heavy ion irradiation, neutron damage, silicon bipolar transistor.

We present a series of metrics for comparison between displacement damage due to heavy ion and neutron irradiation in silicon bipolar junction transistors. We have compared ion and fast neutron irradiations to determine an ion-to-neutron damage equivalence. We find that a combination of metrics (damage factor, Deep Level Transient Spectroscopy (DLTS) and Annealing Factor) are needed to ensure a comprehensive understanding of the physics involved in the ion-to-neutron conversion. The linearity of the damage factor (primarily probing the base-emitter junction) is not enough to ensure a valid comparison; rather, we must also use additional techniques (DLTS and capacitance measurements) to ensure that collector compensation is not occurring. As a result, care must be taken in choosing the irradiation beam for ion exposures. The displacement damage should peak in the sensitive region of the device to both ensure maximum gain degradation and to minimize collector compensation. Index Terms--Damage equivalence, heavy ion irradiation, neutron damage, silicon bipolar transistor.

Results of displacement damage correlation between neutrons, light ions and heavy ions in bipolar junction transistors are presented. Inverse gain degradation as the function of fluence was measured. The inverse gain degradation due to heavy ion irradiation followed the Messenger-Spratt equation, while some deviation was found for light ions. Index Terms--Damage equivalence, silicon bipolar transistor.

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 [micro]m to 70 nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies. Index Terms--Collected charge, heavy ion and proton irradiation, single event transient, SOI and bulk transistors, statistical response, transient current, transient width.

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-[micro]m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency. Index Terms--Collected charge, heavy ion, pulsed laser, SOI and bulk transistors, transient current.

This paper investigates the charge collection mechanisms occurring in heavy ion irradiated metal oxide semiconductor (MOS) devices. The parasitic bipolar effect, inherent to the structure of SOI transistors, is shown to exist in bulk NMOS transistors as well. We experimentally show that the drain junction of an OFF-state bulk MOS transistor collects more charge than an identical junction isolated from neighboring elements. In other words, the proximity of the source junction and the triggering of the bipolar-like structure are responsible of charge amplification. A higher current peak on the drain is observed, and this enhancement effect is high enough to invalidate usual charge collection models based only on funnel and diffusion transport. Thus, the proximity of other junctions has to be considered to improve charge collection model in bulk technologies. Index Terms--Bipolar amplification, bulk and SOI transistors, charge collection, heavy ion irradiation, transport by funnelling and diffusion.

This paper analyzes the collected charge in heavy ion irradiated MOS structures. The charge generated in the substrate induces a displacement effect which strongly depends on the capacitor structure. Networks of capacitors are particularly sensitive to charge sharing effects. This has important implications for the reliability of SOI and DRAMs which use isolation oxides as a key elementary structure. The buried oxide of presentday and future SOI technologies is thick enough to avoid a significant collection from displacement effects. On the other hand, the retention capacitors of trench DRAMs are particularly sensitive to charge release in the substrate. Charge collection on retention capacitors participate to the MBU sensitivity of DRAM. Index Terms--Capacitors, charge collection, charge sharing, device simulation, diodes, DRAMs, heavy ion irradiation, isolation oxides, MBU sensitivity, MOS structures, SOI technology, SRAMs, transient currents, trench capacitors.

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.