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This paper examines how the use of genebank materials has changed from 1996 to 2006 using a similar survey by Dudnik et al. (2001) of reports published in 1996 as a baseline. Articles published in four journals generally used by genetic resource scientists were analyzed in each 2006 issue, as was done by Dudnik et al. in 2001. Studies involving genebank materials were selected and the following data were recorded: species used, locations of studies, affiliation of researchers, sources of the materials and their uses. The analysis identified 320 studies in which a total of 57,935 accessions from 148 genebanks were used. Crop wild relatives were targeted in 20% of the studies. The study showed that a much higher percentage of accessions came from developed (87%) than from developing countries (7 %), while 6% were supplied by CGIAR centers. The results in 2006 revealed an increase in the proportion of studies using genebank materials as compared to 1996. Genebank materials were used primarily for studies of genetic diversity, agro-morphological and nutritional quality characteristics, biotic resistance, and mapping. Of the institutions carrying out the studies, 93% were from the public sector. However, there are still some barriers that limit the exchange of germplasm across borders. This implies that greater awareness among policymakers will be needed tofacilitate the necessary exchange of plant genetic resources between countries to improve agricultural production.

Atherosclerosis (stenosis) is a common cardiovascular disease in which the blood vessel restructures by narrowing, thickening and gets hardened due to the deposition of plaque. A detailed study of narrowing of arteries applying computational aspects which leads to better findings in order to know the underlying mechanics of development and progression of such diseases. Such kind of analysis can be a useful tool for the medical professionals to study the realistic physiological conditions. They can simulate and observe the blood flow in arteries. In the present study, a case of normal and stenosed carotid bifurcation is simulated. The models are generated in CATIA based on the clinical data obtained from a patient using Ultrasound Doppler. A transient FSI analysis considering Newtonian behavior is performed to compare the significance of High Blood Pressure (HBP) and Normal Blood Pressure (NBP) on carotid bifurcation. The FSI simulation is carried out for both HBP and NBP conditions for several pulse cycles on normal and stenosed models using ANSYS13.0 to demonstrate the changes in flow behavior at various sections of the model. The computed results agree well with clinical observations and available literature as seen in case of NBP.

We propose a modified structure of tunnel field-effect transistor (TFET), called the sandwich tunnel barrier FET (STBFET). STBFET has a large tunneling cross-sectional area with a tunneling distance of ~2 nm. An orientation-dependent nonlocal band-to-band tunneling (BTBT) model was employed to investigate the device characteristics. The feasibility of the STBFET realization using a complementary metal-oxide-semiconductor-compatible process flow has been shown using advanced process calibration with Monte Carlo implantation. STBFET gives a high ION, exceeding 1 mA/μm at IOFF of 0.1 pA/μm with a subthreshold swing below 40 mV/dec. The device also shows better static and dynamic performances for sub-1-V operations. STBFET shows a very good drain current saturation, which is investigated using an ab initio physics-based BTBT model. Furthermore, the simulated ION improvement is validated through analytical calculations. We have also investigated the physical root cause of the large voltage overshoot of TFET inverters. The previously reported impact of Miller capacitance is shown to be of lower importance; the space-charge buildup and its relaxation at the channel drain junction are shown to be the dominant effect of large voltage overshoot of TFETs. The STBFET are shown to have negligible voltage overshoots compared with conventional TFETs.

In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors., IEEE

Japan was one of the world's early adopters of broadband Internet access technologies, notably ADSL. Although last year it lost its number one global ranking to China, ADSL deployment in Japan continued to grow. This growth has been tied to ever increasing ADSL bandwidths. Centillium Communications has been in the unique position for many years of a major contributor to this rapid growth, pioneering many new technologies in ADSL, with a ringside seat to observe how competition has stimulated some of these technology advances. This article reviews some of the technologies behind the rapid market growth and provides an overview of directions in which these technologies are shaping the future of ADSL in Japan.

In this paper, for the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for analog and mixed-signal applications. The SH structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent dc output characteristics and experimental characterization results on these devices show better Vth-L roll-off, low DIBL, higher breakdown voltages, and kink-free operation. Further SH SOI MOSFETs have been shown to exhibit reduced parasitic bipolar junction transistor effect in comparison to the homogeneously doped channel (conventional) SOI MOSFETs. Small-signal characterization on these devices shows higher ac transconductance, higher output resistance, and better dynamic intrinsic gain (gmRo) in comparison with the conventional homogeneously doped SOI MOSFETs. Also, the low drain junction capacitance as a result of low impurity concentration near the drain region is beneficial for improved circuit performance. The experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance in comparison with conventional homogeneously doped SOI MOSFETs. From 2-D device simulations, the lower hot carrier degradation mechanism in SH SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs., IEEE

In this paper, we study the stress voltage polarity-dependent reliability of n-channel metal-nitride-silicon field-effect transistors (MNSFETs) with ultrathin jet vapor deposited (JVD) silicon nitride dielectric. Under constant voltage stress, device parameters such as threshold voltage and transconductance degrade. Charge trapping due to interface and bulk traps is observed. Our study shows that the degradation is polarity dependent. MNSFETs show lower degradation under positive stress fields. We have also compared the performance of MNSFETs with conventional MOSFETs under identical stress conditions. Under positive stressing, MNSFETs clearly outperform MOSFETs, but under negative stressing, MNSFETs show more degradation.

In this paper, we have systematically investigated the effect of scaling on analog performance parameters in lateral asymmetric channel (LAC) MOSFETs and compared their performance with conventional (CON) MOSFETs for mixed-signal applications. Our results show that, in LAC MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID etc.) down to the 70-nm technology node, in addition to an improvement in drive current and other parameters over a wide range of channel lengths. A systematic comparison on the performance of amplifiers and CMOS inverters with CON and LAC MOSFETs is also performed. The tradeoff between power dissipation and device performance is explored with detailed circuit simulations for both CON and LAC MOSFETs., IEEE

CASE A 75-year-old man underwent intramedullary nailing for an unstable intertrochanteric fracture of the left hip. After surgery and postoperative recovery, he was transferred to a rehabilitation ward. He was able to mobilize at 2 days postoperatively; at 2 weeks postoperatively, he developed the sudden onset of tachycardia, hypotension, and a large hematoma on the left thigh. Following immediate resuscitation, a computed tomography (CT) angiogram demonstrated a bleed from a branch of the profunda femoris artery. The 3-dimensional CT reconstruction implicated the displaced lesser trochanter osseous fragment as the cause of the hemorrhage. CONCLUSION Surgeons should be aware of this rare complication and the possible etiology of fracture displacement as the cause of a delayed-onset bleed after intramedullary nailing, and they should also be cognizant of the subsequent optimal management.

In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes. We show from experimental and simulation results that when the channel is biased in accumulation and with the drain-substrate junction reverse biased, charge injection is localized in the gate-drain overlap region. Under this localized charge injection (LCI) mode of operation, the gate voltage is a function of edge oxide thickness which in turn can be related to the plasma damage received during the poly-etch and subsequent spacer oxide formation. The detailed mechanism of localized charge injection for a study of plasma edge damage is explained along with the experimental demonstration of this technique using submicron MOSFET's., © IEEE

In this letter, the low-frequency noise performance of single-halo (SH) devices is reported, and the physical mechanisms are identified. Experimental results show that, at constant gate overdrive voltages, SH devices show reduced low-frequency noise levels compared to the conventional devices. However, under constant current bias conditions, the noise reduction is less substantial. Low-frequency noise dependence on channel length is also investigated for SH devices based on the electrical measurements and analytical calculations.

In this letter, we analyze the suitability of the double gate MOSFETs (DG MOSFETs) for RF-mixer applications from the point of optimizing the transconductance gain, power consumption, and area. Mixer topologies using the 0.13-μm conventional MOSFETs, simultaneously driven DG MOSFETs (SDDG) and the independently driven DG MOSFETs (IDDG) are compared using extensive device simulations. In the frequency range 1-40 GHz, our simulation results show that the mixer circuits realized using the SDDG technologies show an order of magnitude lower power-area product, for a given transconductance gain, compared to the conventional and the IDDG technologies., IEEE

With every new technology node, scaling down of Device-to-Interconnect Capacitance ratio causes Interconnect delay to become bottleneck for circuit performance. To miti-gate this effect, interconnect routing area on-chip should be minimized for improved power-delay product. In this aspect, Fin FET with multiple fins per lithographic pitch gains more advantage, in comparison to Planar Device, since, such Fin FET devices allow increase of electrical width without increasing device layout area and thus, interconnect capacitance is comparatively lower. Therefore, minimum delay could be achieved for lesser device width, and thus, with lower power. This paper proves the performance enhancement with such Fin FET Device for Mux Circuit, and aims to find out Optimum Design Space for Mux Circuit, at 22nm technology node, with practical value of Interconnect Capacitive load (extrapolated from circuit layout in current technology node).

A multi-frequency transconductance technique for interface characterization of sub-micron SOI–MOSFETs is implemented. This technique is shown to be highly suitable for interface characterization in SOI devices where conventional charge-pumping techniques cannot be applied. Using this multi-frequency technique, sub-micron SOI–MNSFETs with a SiN dielectric deposited by a novel jet-vapor-deposition (JVD) process are characterized. Results are compared with charge pumping results obtained on bulk MNSFETs with identically processed JVD nitrides.

Using high-k material in a gate dielectric stack, low-operating-voltage organic semiconducting material sensors for determining total dose radiation are proposed. To improve the stability of organic semiconducting layer in the atmospheric conditions, a thin silicon nitride layer deposited by hot-wire CVD process was used as a passivation layer. Furthermore, in order to achieve higher sensitivity, a parallel connection of organic field-effect transistors (OFETs) is explored in this letter. These sensors are exposed to ionizing radiation using a cobalt-60 radiation source for different total dose values. A three-times improvement in sensitivity was observed in the off current with a three-OFET array.

In this letter, the integration of a high-k gate dielectric has been demonstrated for achieving low-operating-voltage organic field-effect transistors (OFETs) and circuits based on solution-processed poly(3-hexylthiophene) (P3HT). We have successfully demonstrated all-p-type organic circuits based on P3HT operating at below 4 V supply voltage. The switching behavior is improved by using the bootstrapping technique, with the boot-strapped inverter showing good results with a dc gain (A(v)) of -1.7 and V(OH) and V(OL) values of 3.3 and 0.35 V, respectively. The output swing of the bootstrapped inverter is improved by about 40% when compared to that of simple all-p-type inverters, as demonstrated by using experimental characterizations.

Pentacene organic field effect transistors are fabricated using polymethyl methacrylate (PMMA) as a gate dielectric on flexible polymeric substrates like the indium tin oxide coated polyethylene terephthalate (ITO coated PET), and polyethylene napthalate (PEN) in top contact configuration. The ITO and aluminium (evaporated on PEN) act as the gate materials for the OFETs. The devices on ITO coated PET show electron mobility up to 0.07 cm2/V-s and the on/off ratios in the order of 103.

In this paper, with the help of simulations the concepts of source/drain (S/D) impurity profile engineering are proposed for reduction of the junction capacitance (Cj). It has been recently shown that it is possible to realize the benefits of PD- SOI technologies with the help of Source/Drain On Depletion Layer (SDODEL) MOSFETs, employing the bulk technologies. Here, for the first time, we investigated analog performance improvement with Single Halo SDODEL MOSFETs, as well as Double Halo SDODEL MOSFET and compared their performances with Double Halo MOSFETs (which will henceforth be referred as Control MOSFETs) with extensive process and device simulations. Our results show that, in Single Halo SDODEL MOSFET there is a significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/I D etc.) for sub 100nm technologies.

Interface state generation and threshold voltage degradation for various channel length devices, stressed at different drain bias conditions, has been studied. It is found that the NBTI (negative bias temperature instability) effect decreases at low drain bias due to decrease in effective gate bias near the drain edge. The subsequent increase in degradation at higher drain stress bias is due to non-uniform generation of interface states and subsequent diffusion of generated hydrogen species along the length of the channel. This effect is more pronounced for short channel devices stressed at high temperatures and high drain bias.

Lateral asymmetric channel (LAC) or single halo devices have been reported to exhibit excellent short channel behavior in the sub-100-nm regime. In this paper, we have quantified the performance degradation in LAC devices due to fingered layouts. Our mixed-mode two-dimensional simulation results show that though the fingered layout of the device limits the performance of these MOSFETs, they still show superior performance over the conventional devices in the sub-100-nm channel length regime. We also present the simulation results of a two-stage operational amplifier with LAC and conventional devices using a 0.13-/spl mu/m technology with the help of look-up table simulations. Our results show that for the given design specifications, an OPAMP layout with conventional devices occupies 18% more chip area compared to the LAC device., IEEE

This paper discusses the effect of localized charge storage on sub-threshold swing and threshold voltage in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cells. By analyzing the change in potential contours, it has been shown that the change in sub-threshold swing is correlated to fringing of electric field lines, and hence to the gate-to-substrate capacitance.

The role of initial interface damage for negative bias temperature instability (NBTI) degradation has been examined for short channel MOSFET devices. In this paper we present a detailed study of the role of initial silicon-oxide interface quality on the NBTI degradation. Hole density and oxide fields are important parameters responsible for NBTI degradation. Our results show that NBTI degradation is independent of initial interface quality.

The desired low power and high speed operation of CMOS integrated circuits is driving force for CMOS scaling into the sub-100 nm regime. In addition to the supply voltage, the threshold voltage needs to be scaled proportionately for low power operation. The idea of a Dynamic Threshold MOSFET (DTMOS), without the associated substrate loading effects, is a key to the problems involved in Sub-100 nm device scaling for low power CMOS. This work focuses on the device optimisation for such low power ULSI circuits using a novel implementation of Electrically Induced Junction (EJ)-MOSFET as a DTMOS. Such an implementation can be used without the additional substrate loading effects and the supply voltage limitations, commonly associated with conventional DTMOS operation. Our detailed DC as well as transient simulation results bring out the advantages of this novel structure.

This paper analyzes in detail the damage generation in n-channel MOS transistors operating in the substrate enhanced gate current (SEGC) regime. The results are also compared with the damage generated during conventional hot carrier stress experiments. Stressing and charge pumping experiments are carried out to study the degradation with different substrate bias. Our results clearly show that the application of a substrate bias enhances degradation, which is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanisms responsible for such trends are discussed.

The effect of channel hot carrier (CHC) stress under typical analog operating conditions is studied for the first time for single halo (SH) p-MOSFET devices. The SH devices show less degradation under identical operating conditions compared to conventional MOSFETs. The effect of SH implant parameters on device degradation is presented.

SOI devices are of great interest, especially for low power and low voltage applications. To achieve this goal, the device threshold voltage must be lowered while maintaining low sub-threshold leakage. However, when devices are downscaled, short channel effects (SCE) and hot carrier effects (HCE) also become severe issues in SOI MOSFETs. Symmetric halo implantations are widely used in bulk MOSFETs to improve SCE. Recently, asymmetric channel implantation or "pocket implantation" on the source end was introduced in bulk MOSFETs to adjust the threshold voltage and improve the device SCE and HCE. In this work, for the first time, we introduce large tilt angle implantation in the SOI MOSFET to form a lateral asymmetric channel (LAC) doping profile after gate formation. High concentration channel doping near the source end reduces DIBL and threshold voltage roll-off while low doping concentration near the drain side ensures high mobility. Furthermore, the peak electric field near the drain is reduced and impact ionization is less serious compared to conventional devices. To reduce the source/drain parasitic resistance, a novel salicide technology with Ge pre-amorphization is used (Hsiao et al, IEEE SOI Conf., p. 126, 1996).

Design For Diagnostics (DFD) is critical for rapid silicon debug of new product and ramping to high volume manufacturing. I feel two aspects of DFD are important. The first enables software fault localization tools that quickly localize to the failing node (this includes ad hoc DFT methods, scan etc.). The second type of DFD enables success with physical localization tools. This includes designed in physical features to enable rapid bug verification with focused ion beam milling, and probe points for internal signal probing. Both types of DFD are needed and complement each other in the different phases of silicon debug and root cause analysis.

The spatial distribution of interface traps in hot-carrier stressed lateral asymmetric channel (LAC) and conventional (CON) MOSFETs have been determined using a novel charge pumping technique. Detailed post-stress interface characterization shows reduced interface-trap buildup and lesser drain current degradation in LAC MOSFETs compared to the CON device, for stressing at different times and drain biases and for all channel lengths down to 100 mn. The interface-trap profile parameters (peak magnitude and spread) have been correlated to drain current degradation as function of stress drain bias and time. It is shown that with increased stress drain bias and time, both the peak and spread of the interface-trap profiles increase, but at different rates. While the peaks evolve identically for CON and LAC MOSFET's, the spreads do not, which is shown to affect the rate of the resulting transconductance degradation differently. Device simulations show a lower peak lateral electric field in LAC MOSFETs compared to CON devices, which is responsible for the observed reduction in hot-carrier degradation in such devices. (C) 2001 . .

Vitamins, such as A, beta carotene, C, E, B12 and folate, are the micronutrients with the strongest evidence of having a link to cancer prevention and control. Deficiency of these vitamins at the dietary, systemic or mucosal level will interact with tobacco use and increase the risk of oral precancerous lesions. The objective of this study was to (1) establish the baseline circulating levels of these vitamins in our normal population with and without tobacco use and (2) compare these levels with the values obtained in cases of oral leucoplakias. 50 normal controls with 25 each in chewers and non-chewers, matched for age and sex, were selected. 50 cases of oral leucoplakias (clinically detectable white patches) from the field constituted the study group. Simultaneous measurement of serum vitamin B12 and folate were carried out by radioassay. The other serum vitamins were estimated spectrophotometrically. Except for serum vitamin E, all the other serum vitamin levels were significantly decreased in oral leucoplakias compared to the controls. Cancer chemopreventive agents acting as inhibitors of both initiation and promotion, as analysed in our population, is promising for further intervention trials.

Unlike the impressive advancement of cancer risk assessment, the "cutoff approach" based on hazard quotient in noncancer risk assessments recommended by the EPA has crucial deficiencies. Several alternative approaches have been suggested in the literature to modify the noncancer risk characterization based on reference doses. Recent studies have indicated that the effects of perchloroethylene (PERC) on the central nervous system (CNS) is a much more sensitive noncancer endpoint than cancer which is currently the basis for deriving its public health criteria and standards. Studies indicate that 20 ppm of inhaled PERC concentration elicited adverse effects on the CNS in experimental animals and humans. However, the existing EPA oral reference dose (RfD), a noncancer toxicity parameter for PERC (0.01 mg/kg/day), is based on the induction of hepatotoxicity and increased body weight gain induced by PERC in rats. An attempt was made in this paper to examine whether logistic regression of dose-response data could be applied to assess the noncancer risks. In order to perform logistic regression the inhalation toxicity data of PERC were classified according to the severity of toxicity paradigm used in toxicity analysis. Based on the sensitive noncancer endpoints identified from severity classification, a logistic regression analysis of the data was performed and its potential applicability in noncancer risk characterization was described for workers exposure to PERC in dry-cleaning operations.

A questionnaire about the use of prophylactic antibiotics in bacterial meningitis was sent to medical officers of environmental health and microbiologists in England. There was broad agreement that prophylaxis should be offered to close contacts of acute meningitis due to Neisseria meningitidis but not to contacts of meningitis caused by Streptococcus pneumoniae. Overall 28% of those who replied said they could consider giving prophylaxis to contacts of meningitis due to Haemophilus influenzae. Rifampicin was the most common choice of drug. The indications for prophylaxis in bacterial meningitis are discussed.

Remote sensing activities in India over the past decade are briefly described in the paper; some important application areas are explained. Some results are highlighted. Activities in India for building remote sensing spacecraft, sensors and ground segment are summarised. Some facilities in India for remote sensing applications including low cost interpretative equipment developed are described. The paper also outlines the Indian Remote Sensing Satellite (IRS) series, the first of which is presently under development for launch in 1986 and the National Natural Resources Management System (NNRMS) under evolution.

In this investigation minimum weight design of wing structures with restrictions on strength, stability and frequency characteristics is attempted. The multiweb delta wing structure is idealized with three different kinds of finite elements. The constant stress triangular plate elements, the rectangular shear panels and pin jointed bar elements are used to represent, respectively, the cover skins, webs and the stringers of wing structures. A parametric study is made to reduce the number of design variables which in turn reduces the required computational effort. The feasibility of employing linearly approximated redesigns is investigated. Numerical results are presented to illustrate the feasibility. Off-design charts have been obtained by performing sensitivity analysis about the final optimum design point.

For the first time, we report a study on the hot carrier reliability performance of single halo (SH) thin film silicon-on-insulator (SOI) nMOSFETs for mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and a low impurity concentration in the rest of the channel. Besides having excellent DC output characteristics, better V/sub th/-L roll-off control, lower DIBL, higher breakdown voltages and kink free operation, these devices show higher AC transconductance, higher output resistance and better dynamic intrinsic gain (g/sub m/R/sub 0/). Experimental results show that SH SOI MOSFETs exhibit a lower hot carrier degradation in small-signal transconductance and dynamic output resistance, in comparison with the conventional (CON) homogeneously doped SOI MOSFETs. From 2D device simulations, the lower hot carrier degradation mechanism in SH-SOI MOSFETs is analyzed and compared with the conventional SOI MOSFETs.