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True Random Number Generator (TRNG) has become a central element of today’s secure communication. TRNGs developed through FPGA implementation have a significant role in a number of applications in multimedia communication. Ring Oscillator (RO) has been adopted extensively for developing device-independent TRNG structures. The proposed design is a generic TRNG architecture based on an arrangement of ROs with post-processing. This TRNG was initially tested on Altera Cyclone II FPGA which consumed only 64 inverters to produce good randomness. Also, the device-independent capability of this design has been verified by implementing it on other two FPGA families Xilinx Artix – 7 and Microsemi Smart Fusion2. True randomness was also verified by conducting restart experiment, and the statistical properties of TRNG were evaluated through entropy analysis and NIST SP 800–22 tests. The proposed TRNG yields 26.640650 Mbps as throughput with a sampling clock of 27 MHz. Going beyond the regular key generation utility, the evolving random bits of TRNG were packed suitably to perform confusion of grayscale images producing a near-zero correlation of pixels, thereby extending the application of TRNG to image encryption.

Microprocessors are regarded as the “heart” of an operating system. Arithmetic and Logical Unit (ALU) plays a crucial role in microprocessors, taking care of all critical tasks. Thus, considering the varied applications of the microprocessor, the security of the data and the operations performed by the microprocessor is critical. Field Programmable Gate Array (FPGA) stands in its outstanding capability due to its field re-programmability unlike the semi-custom and full-custom designs. It has also has the capabilities of parallel processing, and its ability to process data high speeds due to its high clocking frequencies. Thus, FPGA can be a fruitful prototyping agent for Microprocessors. In this work, a lightweight pipelined computational unit (ALU), an important part of the microprocessor, has been realised on Intel Cyclone V FPGA using Verilog HDL. The lightweight computational unit also includes an optional lightweight S-Box that can provide adequate non-linearity and security to the data. Also, a custom testbench has been designed for functional verification. The optimised design occupies 515 logic elements and dissipates 199.75 mW of power when including the memory. Further, it takes four clocks as an accumulation period to initialise the pipeline and produces the computational results for every subsequent instruction at the same clock instant.

Due to the emerging high-speed digital infrastructure, the protection of data being shared throughout the open networks has been a challenging task. By large, the dependency on cryptographic primitives exists to encounter cyberspace challenges. Key generation is a core process of any cryptographic application which improvises the strength of the algorithm. Reconfigurable hardware-assisted true random number generators (TRNGs) play a crucial role in key generation to provide high-speed cryptographic solutions. In this work, metastability-influenced TRNG architecture on Altera Cyclone II EP2C20F484C7 FPGA has been proposed. The 256 units of SR latches with de-synchronisation technique were the prime source used to harvest the true randomness. TRNG design consumed 1851 logic elements with a dynamic power dissipation of 4.41 mW. Proposed architecture achieves a high throughput of 26.64065 Mbps using 27 MHz onboard sampling clock. This TRNG has been validated through entropy, correlation, NIST SP 800-22 batteries of test, linear complexity test, restart experiment and hamming distance analysis.

The emerging growth in communication arena firmly demands a secure channel and needless to mention that security and privacy of the user are the top priorities in audio communication. To transmit audio signals safely, cryptography is being adopted widely. Chaos-based cryptography is one of the effective strategies that attract researchers to develop more techniques. Characteristics of chaotic systems such as ergodicity and stochasticity are the main motivators for using them in encryption schemes. This work presents an field programmable gate array (FPGA) governed chaotic audio encryption scheme based on Lorenz attractor. This scheme of encryption undergoes two consecutive steps of operations, namely confusion by linear feedback shift register (LFSR) and diffusion through the random numbers generated in X, Y, and Z planes of the chaotic attractor. A study has also been carried out to analyze the best diffusion from the obtained results. Evaluation of the proposed scheme includes entropy, correlation, histogram, PSNR, and MSE. Further, NIST SP 800-22 batteries of test have been performed to ensure that the encrypted audio data possesses more randomness. Moreover, this work consumed 15,422 logic elements and 14.22 mW of dynamic power to accomplish the design. Noticeably, the proposed work has achieved 10.346 Mbps as a throughput to encrypt 216 × 16 bit samples of audio data.

In recent years, encryption of medical images has been given much importance and several cryptographic algorithms and principles have been made and designed for secure communication. One such approach has been proposed in this work using pixel scrambling and diffusion techniques governed through linear feedback shift register (LFSR) and modified logistic map (MLM). The main advantage of this work is its concurrent encryption through which the scrambling and diffusion have been performed on the fly without any additional delays. The proposed design has been implemented on Intel Cyclone IV E FPGA using Quartus II Electronic Design Automation (EDA) tool. Further, the functional verification of LFSR and MLM has been carried out through ModelSim simulation. The design occupies 3580 logic elements and 135 logic registers to encrypt 256 × 256 × 16 bits of DICOM image at 216 mS when it was operated with 50 MHz frequency. Also, this work achieves near-zero correlation, and the statistical properties of the encryption have been tested through standard metrics.

This paper presents a true random key generation using Physically Unclonable Function (PUF). PUFs are considered as "physical fingerprint" of anys Integrated Circuit (IC) through which they can be differentiated from others. They offer a plenty of applications namely Hardware authentication, Identification, Anti – counterfeiting to safeguard the hardware as well as the sensitive data being processed or stored in the hardware. A deeper insight is required into the design and implementation of hardware efficient FPGA based PUF with a focus on low area overhead. In this work, PUF architecture for key generation on Intel Cyclone II FPGA using Verilog HDL and Quartus II 13.0 Electronic Design Automation (EDA) tool has been proposed. SR latch based metastability is the main concern of PUF generation. Metastability on SR latch act as entropy source to generate true randomness. This design requires only four SR latches to produce adequate true randomness. Further, true randomness is extracted through harvesting mechanism where Meta beat counting and De - synchronization techniques have been investigated with respect to equidistribution property. Post processing unit has been incorporated to enhance the statistical properties of PUF. This design consumes 881 logic elements and dissipates 4.41 mW of power for implementing the PUF architecture on Cyclone II EP2C3F484C7 FPGA. Entropy, restart experiment and NIST SP 800 – 22 tests have been performed to evidence the true randomness.

Image encryption is being employed as an important security provider to facilitate the communication of confidential images over various confidential networks. In this work, a RGB image encryption procedure based on Chaotic and Cellular Automata (CA) attractors is proposed. Lorenz, Lu and Rule 42 of CA have been used as encryption mediums in red, green and blue planes respectively. Besides scrambling and XORing operations on secret image, a random synthetic image has also been used for diffusion on the three planes. Cyclone II FPGA EP2C35F672C6 has been utilized to generate the low correlation yielding random synthetic image aided by beat frequency detection using PLLs and diffused bit generation process. The proposed approach satisfies the various statistical parameters and offers tangible resistance to differential, occlusion and chosen plain text attacks on RGB images.

In the Quaternary era, the increased development in the medical field leads to the concern towards the authentication and security of the medical images. Sharing and transmission of DICOM image using a high secure encryption is challenging. To enhance high security, the confusion and diffusion techniques are employed. More chaos is brought out by introducing discrete chaotic maps such as logistic or tent map and continuous attractor like Lorenz attractor. To validate the algorithm several analyses such as brute force, statistical and cropping attacks are carried out to prove the effectiveness of the proposed work.

Now a day, the transmission of digital files over the insecure medium such as the internet has been increasing tremendously. The cyber criminals can hack the informative data which are being transmitted through the open network. In such a scenario, security became a crucial factor in safeguarding the information in all sectors such as business, government etc. In this paper, a novel digital image encryption is proposed based on the key generated from chaos-based Lorentz attractor. At first, a confusion and diffusion operation is done in the low-frequency band of DWT transformed digital image to get a random cipher image. To enhance the security level, a 14-bit LFSR is designed on Cyclone IV E, EP4CE115F29C7 FPGA board to generate the synthetic image. As the final stage of the algorithm, diffusion is performed based on XOR operation between the random cipher image and a synthetic image to get a final encrypted image. The designed image encryption algorithm is validated by performing statistical test, error metrics and key space analyses. The developed algorithm has achieved entropy equals to 7.9965; PSNR is 8.9903 which prove the algorithm is secure from the exhaustive attacks.

True Random Number Generators (TRNGs) became the basic building block of modern cryptography. Though most of the noise source of TRNGs is analog circuit, to provide compactness and high throughput, hardware based TRNG solutions are recommended. This work aims at the generation of true random bits through beat frequency detection influenced by identical length of ring oscillators on FPGA. The main idea of this work is to extract the true randomness from one jitter clock produced by a ring oscillator through another jitter clock generated by the second ring oscillator. To enhance the randomness, Von Neumann Corrector (VNC) post processing is utilized. Proposed TRNG is designed using VHDL and Quartus II 8.0 EDA tool. It consumes 523 combinational functions and 539 logic registers on Altera Cyclone II EP2C20F4S4C7 FPGA where it achieves the throughput of 26.640650 Mbps when 27 MHz is used as sampling clock. Statistical efficiency of the TRNG is evaluated using entropy, correlation and NIST SP 800 -22 analyses. True randomness of the TRNG is verified through restart experiment.

Defined Radio is an all new technology being developed in the 21 st century. Over a past couple of decades many Mobile communication standards have evolved and even today researches are going to develop new standards. Different standards of Mobile communication use different type of hardware circuitry. The existing mobile communication standards are primarily regional and not global. So efforts are going on to develop systems which can support multiple mobile communication standards using same hardware but swapping the software. The main aim of this paper is to develop a model of a Software defined Radio using SIMULINK tool to implement the IEEE 802.11 standard and the Bluetooth standard. The main aim of this paper is to build various protocols for WLAN and the Bluetooth standards and to demonstrate their functionality. This includes implementation of IEEE 802.11a standard for the WLAN and basic core protocols for the Bluetooth. According to the IEEE 802.11a standard out of the various transmission modes the basic transmission mode (BPSK with 6Mbps transmission speed) was implemented. For forward error correction half convolution codes are used. The communication channel is assumed to be flat fading channel where the transmitted sub carrier undergoes flat fading. The ideal channel model for this type of channel is chosen as Nakagami channel. Regarding the Bluetooth technology all the core protocols of Bluetooth are implemented and the type of modulation is Gaussian phase shift keying and frequency hopping spread spectrum.

Identifying and eliminating the limitations in the existing security systems by using the image based retrieval technique to provide an exquisite security application based on facial recognition to approve a person's identity. This security system gets a live query image and stores it temporarily into the database where the predefined images are already stored. A (energy) signature for key image as well as the pre- defined images are generated and then they are compared using the Euclidean distance algorithm and conclude whether a person is authorized or not.

Hepatitis A (HAV) infection is one of the most common forms of hepatitis in the paediatric age group in developing countries. It is usually self-limiting and rarely accompanied by extra hepatic complication. In this article, we report two children with hepatitis A who had associated issues of pleural effusion and ascites. Both issues improved with resolution of hepatitis after symptomatic treatment. Although uncommon, extra hepatic manifestations can occur with hepatitis A. However, they resolve completely. Paediatricians in developing countries should be aware of this rare association to avoid unnecessary investigations.