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Nowadays, since most information is transmitted by public medias, the security of information is very important, especially of confidential information. The information security system has its particular processing method. The use of cryptographic machine is one of the effective solutions. The hidden trouble of cryptographic machine mainly comes from information processing kernel program and key chip. And in China, information security is being menaced, for most of the key chip involving the information security devices come from abroad. Developing the key chip-set for information security system is a hard and chief task for China. A research on system-level architecture of single-chip cryptographic data processing is presented. The architecture involves microprocessor core architecture, data interface, user ID interface, special component for cryptographic data processing and cryptographic algorithms RSA and CHES VLSI implementation IP module and the true random number generator. All of the functions are necessary for the system on a single cryptographic data processing chip. The architecture, including microprocessor core architecture, is incompatible with any other system, and has a special function to accelerate cryptographic data processing, so it is a very effective way to implement information security chip.

Accumulator, as the key element in NCO, can be designed in pipelined structure to increase clock frequency. But regular pipelined structure brings about the logger latency. In this paper a novel design is presented, that uses carry-save addition and carry-feed unit in an accumulator and as a result the latency has been improved considerably.

With the rapid progress of information technology, security becomes one of the key factors in information storage, communication and processing. For the reason of speed and security, the requirement for VLSI chips or modules that support data encryption and decryption increases rapidly. The design and implementation of a data ciphering processor (DCP) chip adopting block cipher algorithm is demonstrated in this paper. The cipher algorithm is qualified for commercial use. The plaintext, ciphertext and key are all 64-bit long. A top-down design flow is used in the implementation. Several methods are employed to enhance the security of the chip. A standard-cell library is also developed in the design. All the design and implementation of this DCP are performed in China. A 0.9um double-layer-metal CMOS technology is adopted for manufacture. The chip achieves the required result in the first time implementation. The encryption/decryption processing speed reaches 40MBit/s.