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Author(s): Kinoshita, Shotaro; Cortright, Kelley; Crawford, Allison; Mizuno, Yuya; Yoshida, Kazunari; Hilty, Donald; Guinart, Daniel; Torous, John; Correll, Christoph U; Castle, David J; Rocha, Deyvis; Yang, Yuan; Xiang, Yu-Tao; Kolbaek, Pernille; Dines, David; ElShami, Mohammad; Jain, Prakhar; Kallivayalil, Roy; Solmi, Marco; Favaro, Angela; Veronese, Nicola; Seedat, Soraya; Shin, Sangho; Salazar de Pablo, Gonzalo; Chang, Chun-Hung; Su, Kuan-Pin; Karas, Hakan; Kane, John M; Yellowlees, Peter; Kishimoto, Taishiro | Abstract: BackgroundDuring the COVID-19 pandemic, the use of telemedicine as a way to reduce COVID-19 infections was noted and consequently deregulated. However, the degree of telemedicine regulation varies from country to country, which may alter the widespread use of telemedicine. This study aimed to clarify the telepsychiatry regulations for each collaborating country/region before and during the COVID-19 pandemic.MethodsWe used snowball sampling within a global network of international telepsychiatry experts. Thirty collaborators from 17 different countries/regions responded to a questionnaire on barriers to the use and implementation of telepsychiatric care, including policy factors such as regulations and reimbursement at the end of 2019 and as of May 2020.ResultsThirteen of 17 regions reported a relaxation of regulations due to the pandemic; consequently, all regions surveyed stated that telepsychiatry was now possible within their public healthcare systems. In some regions, restrictions on prescription medications allowed via telepsychiatry were eased, but in 11 of the 17 regions, there were still restrictions on prescribing medications via telepsychiatry. Lower insurance reimbursement amounts for telepsychiatry consultations v. in-person consultations were reevaluated in four regions, and consequently, in 15 regions telepsychiatry services were reimbursed at the same rate (or higher) than in-person consultations during the COVID-19 pandemic.ConclusionsOur results confirm that, due to COVID-19, the majority of countries surveyed are altering telemedicine regulations that had previously restricted the spread of telemedicine. These findings provide information that could guide future policy and regulatory decisions, which facilitate greater scale and spread of telepsychiatry globally.

This dissertation includes three chapters that cover topics on international trade. The first chapter focuses on various production strategies of multinational firms and presents a complex global sourcing model. Multinational firms have been the driving force of growing global production over the past decades. With multinational firms’ Foreign Direct Investment (FDI), international trade is engaged on the firm level, rather than on a country or industry level. However, their production strategies are not limited to FDI. One option would be arms’ length contracts, so-called outsourcing, even though firm productivity determines the sourcing strategies. In this paper, we extend the range of complex global sourcing strategies used by multinational firms, in which they utilize outsourcing as an additional strategy and connect it to the location choice. The analysis reveals that the equilibrium regime of firms is determined by industry characteristics such as the relative fixed costs and the outsourcing related parameter. Along with firm productivity, the results show the implications of self-selection into FDI versus outsourcing.The second chapter provides the welfare implication of heterogeneous multinational firms by using a general equilibrium simulation model. We extend the model presented in the first chapter to the general equilibrium and quantify the gains from trade, comparing them with the trade-only model. The gains from trade liberalization can be higher with both trade and multinational firms than with only trade. The income path induced by multinational firms is a significant factor in explaining the gap of gains across models. FDI by multinational firms can re-organize the foreign factor market that drives the welfare gains to respond more sensitively in our model than with the trade-only model. Additionally, our model implies that welfare responses differ, depending upon the production boundaries.In the last chapter, we discuss the recent Korea-Japan trade dispute in 2019. This work primarily focuses on quantifying the economic impacts of the dispute and how much it creates trade diversion with their major trading partners. Using the GTAPinGAMS model calibrated to the latest GTAP 10 database, we consider the non-tariff barriers in our model—the export controls by the Japanese government and boycotts by Koreans. We control bilateral trade shocks to reflect the observed trade responses in the Korea Customs Service data. We analyze the impacts of the trade dispute on welfare, sectoral outputs, and trade patterns. Our results show that the trade dispute impacts Korea the most, and Japan is followed. The welfare impacts estimated in this study would be 0.14% ($1033.71 million) for Korea and 0.01% ($345.69 million) for Japan. Additionally, the trade dispute between the two countries creates slight trade diversion with their major trading partners, such as China, the United States, the EU, and Asian countries. Consequently, Japan loses by 2.46% of its trade flow to Korea while slightly increasing exports to other countries. On the other hand, Korea’s imports from Japan decrease moderately, but the trade flow with other countries increases, so that the total percent changes in imports would be 0.18%. Even though the dispute might be initiated and justified by the complicated historical and political reasons between two countries, the results in this work show that the economic impacts are not negligible, which have direct trade policy implications for understanding and restoring the relations.

With the development of cloud technology, people are focusing on lightweight container technology. Container networking is a core technology in providing high-level cloud services, and there are various implementation models such as Container Network Model (CNM) and Container Network Interface (CNI). Among them, CNI is a de-facto standard adopted by various container platforms. There are many plugins that implement the CNI networking model, and the implementation method differs, showing a great difference in a view of performance. MEC (Multi-Access Edge Computing) is a technology that provides services by locating the server closest to the user who wants to use mobile communication services. In this paper, the performance was measured by applying various CNI network plugins to the CoV architecture. Through this measurement, we analyzed the factors of network performance degradation. The result of the analysis is expected to be used as a good reference in constructing the CoV architecture for low latency in the future.

Rapid evolution of Internet of Things (IoT) devices places new demands on the ease of networking very large numbers of devices. The IEEE 1451 family of smart transducer standards for sensors and actuators is evolving to keep pace. One of the most important innovations within the standards is the transducer electronic data sheet (TEDS), which conveys essential device information. For distributed networks, the health of devices is of increasing concern as a means to for assuring measurement and control actions. This paper describes the adaptation of the TEDS concept to a health electronic data sheet (HEDS) that is to be proposed as part of ongoing standards update activities. The HEDS has a lexicon of anomalies and associated measures, which an application can access to support the health functions. Pushing the use of HEDS to edge devices can distribute health assessment across all levels of a system hierarchy.

Encrypted image-based reversible data hiding methods have recently been introduced to conduct research on data encryption. In these methods, an image provider generates encrypted images that are supplied to a data sender. The data sender embeds secret data into the images in order to securely communicate with a data receiver. The data receiver can extract secret data and recover the cover image from the encrypted images. Past research has shown that attackers can easily become suspicious in such cases since all images are scrambled during communication. In this paper, we propose a reversible data hiding method that uses meaningful encrypted images. The proposed method is independent from image provider, data sender, and data receiver respectively by separating the images used and the secret data hidden from each other. In addition, the proposed method reduces distortion during image encryption, and features a data embedding scheme to conceal the existence of secret data from attackers. Experimental results show that the proposed method has high embedding capacity and yields satisfactory image quality with a meaningful image.

To realize a flexible and ultra-low power non-volatile resistive random access memory (NVRRAM), we propose a 3 × 3 resistive memory array comprised of crossbar memristors and a pull-up resistor connected to each column bar (1R-CM). This architecture forms a voltage divider network, which directly reads a parallel data of a row in the form of voltage instead of current. In the proposed structure, the optimum value of the pull-up resistor was found to be 10 MΩ. Poly(4-vinylphenol) (PVP) material is utilized in the memristor to achieve high OFF/ON resistance ratio of ∼1000 as a high resistance state (HRS) is 10 GΩ and a low resistance state (LRS) is 10 MΩ. The operating voltage for writing and reading are ±2 V and 0.5 V in current bound of 10–100 nA, respectively, and consumes ultra-low power (

Malware is any malicious software to cause damage to computer systems. Data hiding is related to hide the secret data without existence of the secret data to the third parties. Recently, data hiding methods are used to intrude anti-virus programs without detection. In this paper, structure of documents are analyzed to embed secret message and the embedding and extracting algorithms are proposed in documents. The experimental results show that the proposed method can hide the secret message into documents and extract the secret message in the receiver side without extra information.

The previous secret image sharing schemes did not provide a copyright and privacy for cover images. The reason is that a dealer selects a cover image by itself and embeds directly the secret data into the cover image. In this paper, a reversible secret image sharing scheme in encrypted images is proposed in order to provide the copyright and privacy of the cover image. We divide a role of the dealer into an image provider and a data hider. The image provider encrypts the cover image and transmits the encrypted image to the data hider, and the standard stream cipher as one-time pad (OTP) with a random secret key is used. The data hider embeds the secret data into the encrypted image, and the encrypted shadow images are transmitted to the corresponding participant. We utilize the polynomial arithmetic operation over GF(28) during the sharing of the encrypted shadow images, and the coefficient of the highest-order term is fixed to one in order to prevent the overflow and the security problem. In the reconstruction procedure, the secret data can be extracted and the cover image can be reconstructed exactly from t or more encrypted shadow images with Lagrange interpolation. In experimental results, the proposed method shows that the PSNR is sustained close to 44 dB regardless of the embedding capacity, where the embedding capacity is 524,288 bits on average.

This paper proposes a novel reversible secret sharing scheme using AES algorithm in encrypted images. In the proposed scheme, a role of the dealer is divided into an image provider and a data hider. The image provider encrypts the cover image with a shared secret key and sends it to the dealer. The dealer embeds the secret data into the encrypted image and transmits encrypted shadow images to the corresponding participants. We utilize Galois polynomial arithmetic operation over 2 and the coefficient of the higher-order term is fixed to one in order to prevent the overflow. In experimental results, we demonstrate that the PSNR is sustained close to 44dB and the embedding capacity is 524,288 bits.

By utilizing electro-hydrodynamic (EHD) technique, we propose an organic non-volatile memory cell capable of storing one bit data. It consists of an organic resistor and a memristor, which stores a bit in the memristor and be read by a voltage divider operation. The proposed device is fabricated by utilizing the materials poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) for resistor and zirconium dioxide ( ZrO 2 ) for memristor. The fabricated device is in the size of 4 mm × 2 mm, and thickness of the memristor and the resistor are 76 nm and 1 μm, respectively. To verify the device, reliable read/write operations are presented for more than 100 cycles. The device is also measured a stable performance against bending, and a minimum applicable bending diameter is 12 mm. The device is analyzed for surface morphology by taking SEM images.

A time-based analogue-to-digital converter (ADC) that can exhibit both low power and high resolution is introduced. By amplifying alternate time residues and successively subtracting the comparator-induced timing offset, both fast conversion speed of 2N cycles for an N-bit converter and very small input-referred timing offset are achieved. For a 12-bit ADC implemented in a 0.18 µm CMOS process, an effective number of bits of 10.8 has been measured at a sampling frequency of 100 kHz, while consuming 30 µW of total power.

This paper presents the effects of infrared energies on dual elliptical nondispersive infrared (NDIR) ethanol gas sensors for preventing drunken drivers and the advantages of using dual ethanol detectors for temperature compensation algorithm. In order to achieve long-term reliability according to the aging of infrared source, two ethanol detectors are placed at the two foci of ellipsoids and the averaged voltage ratios of two ethanol detectors are used to establish the compensation methods.

A modular compact model for memristors which describes a wide range of memristive devices is presented. Its modular structure enables the modeling of various device behaviors by adopting different functions inside the comprising blocks. Rooted from the theoretical analysis on ideal memristors, the window function of the model is uniquely based on the constitutive relationship between charge and flux. This not only solves the stability issue from previously reported models, but also reveals that an equivalent charge-flux constitutive relationship can always be obtained from a variety of memristive devices. Simulations on three types of memristive devices demonstrate that the model is able to reflect common memristive device properties such as limited memristance switching range, linear/nonlinear memristance switching rate, threshold voltages for SET/RESET, nonlinear I-V characteristics, and device parameters with variations.

Shamir`s (k,n)-threshold secret sharing scheme is not secure against cheating by attacker because the signature of participants is omitted. To prevent cheating, many schemes have been proposed, and a proactive secret sharing is one of those. The proactive secret sharing is a method to update shares in the secret sharing scheme at irregular intervals. In this paper, a proactive image secret sharing scheme over is proposed for the first time. For the past 30 years, Galois field operation is widely used in order to perform the efficient and secure bit operation in cryptography, and the proposed scheme with update phase of shadow image over ) at irregular intervals provides the lossless and non-compromising of secret image. To evaluate security and efficiency of images (i.e. cover and shadow images) distortion between the proposed scheme and the previous schemes, embedding capacity and PSNR are compared in experiments. The experimental results show that the performances of the embedding capacity and image distortion ratio of the proposed scheme are superior to the previous schemes.

A compact circuit model and physical hardware emulation for floating memristors are presented. By utilizing memristor 'resistance' as a state variable, and constructing a hardware emulator using a low-complexity modular structure, the model-based emulation can replicate diverse behaviors of different device types. Our hardware emulator for a voltage-actuated, threshold sensitive, two-terminal, floating memristor demonstrates experimentally memristor dynamics. The emulator is capable of computing any arithmetic operations without any disturbance associated with composition of modular structures.

Content Addressable Memory (CAM) is beneficial to applications that require high-speed pattern searching as it provides fast associative lookup operations. As the amount of data to search continues to grow, reducing power consumption while minimizing the costs for speed and area is the main thread of research in designing large capacity CAMs. In this work, we are presenting an active memory architecture incorporating a searchable resistive memory. The proposed architecture incorporates processing logic in close proximity to the RRAM and the RRAM-based TCAM, where the unit TCAM cell is comprised of five transistors and two memristors. Analyzed and simulated performance (e.g., latency, energy consumption, and storage density) of the RRAM-based TCAM at various technology nodes are presented and compared to those of prior CAM/TCAM designs.

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 + 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion step*W).

This brief presents a stateful logic gate based on memristive devices that functions as high-fan-in NOR gates. The proposed logic structure executes multiple implications concurrently in a single step and thus enables fast logic operations reducing the number of pipeline steps. By mapping the logic units to the field-programmable nanowire interconnect fabric, a reconfigurable 2-D logic array for general-purpose functions can be implemented by configuring nanowire crossbar switches.

This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristor's fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution.

With the view towards future non-volatile random access memories that can be integrated at a large scale, extensive study on resistive switching (RS) devices arranged in a crossbar array is currently underway. Although the crossbar array architecture offers relatively simple and acceptable scalability, the presence of sneak current is recognized as a critical issue that needs to be resolved at the device level. In addressing this issue, we demonstrate a new type of RS device fabricated by combining graphene oxide (G-O) and zinc oxide (ZnO) with current-voltage (I-V) characteristics highly-asymmetric depending on the polarity of bias voltage. The distincitve highly-asymmetric I-V characteristics result from the presence of a hetero-junction interface formed beween the G-O and ZnO layers. This hetero-junction manifests resistnace in the range of GΩ under both forward and reverse bias voltage when the device is in the OFF state, in contrast, when the device is in the ON state, it exhibits resitance in the range of MΩ or kΩ under forward bias and GΩ under reverse bias, respectively. We propose to employ demonstrated RS devices with highly-asymmetric I-V characteristics to mitigate adverse effects of the sneak current.

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.

The security of most of the cryptosystems depend on the secret key generator. However, implementation for hardwares, of this key generator is inefficient because secret key generators depend on mathematical problem to generate the high randomness quality. Cellular automata (CA) pseudorandom number generator (PRNG) is more efficiently implemented rather than mathematical problem based PRNGs because a structure of CA PRNG is highly regular and simpler than the other PRNGs. In this paper, a virtual three-dimension (3D) CA PRNG based on the Moore neighborhood structure is proposed. The proposed PRNG uses new methods which are the rule numbering function that provides a high-quality randomness and cell position function that diminishes correlations between global states. In order to evaluate the quality of randomness, the ENT and DIEHARD test suites are used. The results of these tests show that the quality of randomness is superior to previous PRNGs.

We measured the capacity for VoIP traffic in an IEEE 802.11b wireless testbed and compared it with the theoretical capacity and our simulation results. We identified factors that have been commonly overlooked in past studies but affect experiments and simulations. We found that in many papers, the capacity for VoIP traffic has been measured via simulations or experiments without considering these factors, showing different capacity in each paper. After these corrections, simulations and experiments yielded a capacity estimate of 15 calls for 64 kb/s CBR VoIP traffic with 20 ms packetization interval and 38 calls for VBR VoIP traffic with a 0.39 activity ratio. Furthermore, we measured the capacity for VoIP traffic using each access category introduced in the 802.11e standard and the effect of the TCP traffic on VoIP traffic. We found that while the 802.11e standard can protect the QoS of VoIP against TCP traffic, it does not improve the capacity due to the significant retransmissions during TXOP.

This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60deg. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-mum CMOS process, our circuit takes 30 mus to reject the frequency offset of +200 kHz within the accuracy of plusmn5 ppm, with 60-DFFs for a time-to-digital converter

An experimental 2.4-GHz CMOS radio composed of RF and digital circuits for the low-power and low-rate preliminary IEEE802.15.4 WPAN is reported, consuming 21 mW in receive mode and 30 mW in transmit mode. The RF design focus is to maximize linearity for a given power consumption using linearization methods which lead an order of magnitude improvement in LNA/mixer IIP3/power performance. Chip-on-PCB technology allows implementation of a coin-sized radio at very low cost, which also provides 3 dBi gain patch antenna and high Q (>50) inductors.

A high output power VCO (voltage controlled oscillator) in U-band is implemented using 65nm CMOS process. The proposed VCO uses MTM(meta-material) technique with transmission line to increase output voltage swing and overcome the limitation of the CMOS technologies. Two varactor banks widen frequency tuning range upto 5%. The VCO operates at 51.55∼54.18GHz and the measured phase noise is −100.67dBc/Hz at 10MHz offset. The chip area is 0.16×0.16mm2 and the output power is 0.44dBm. The power consumption is 33.6mW with 1.2V supply voltage. The measured FOM P is −181dBc/Hz.

A memristors-based Ternary Content Addressable Memory (mTCAM) is presented. A unit mTCAM cell consists of 5T2R, five transistors and two memristors to store the ternary information, having higher storage density than conventional CMOS TCAMs together with the memristors' unique non-volatility. In the write mode, each memristor in the cell is programmed individually such that high impedance is always present between searchlines to reduce the direct current. A two-step write scheme is proposed to reduce the write voltage compliance, and the search voltage used to drive the search content was chosen to optimize the sensing margin. Simulation results for a 2×4 mTCAM array demonstrate the functionality and feasibility of the proposed mTCAM structure, in both write and search modes.

This chapter reviews recent technology, circuits, and systems trends in memristive electronics, with particular attention to ultra-dense and energy-efficient resistive logic gates and signal processing. A reconfigurable nonvolatile computing platform that harnesses memristor properties is devised to deploy massive arrays of nanoscale resistive memory devices and advance their computing capabilities with much lowered energy consumption than the conventional charge-based VLSI systems. With application of memristive devices for stateful logic gates and multipliers, nonvolatile latches with high integration density and CMOS compatibility, combining the memristor technology with the prevailing CMOS technology pose. To prolong the Moore’s Law beyond the hitherto observed technological limitations.

This paper introduces a memristor-based neuronal spike event generator, in which the memristor models the nonlinear behavior of opening and closing of sodium and potassium ion channels. The neuronal action potential describing both the integrate-and-fire spiking events and the refractory period of nerve membrane cells is enabled by utilizing dual time-constants offered by the bistable resistance state of practical memristive devices. A memristor macromodel which is capable of representing both the threshold effects and boundary assurance is also presented.

In cloud computing, the lightweight, efficient and secure authentication scheme is needed because it is to handle large amounts of data in real-time. Hence, this paper proposes an efficient and lightweight multi-user authentication scheme based on cellular automata (CA) in cloud computing environments. In the proposed scheme, an authentication process is securely performed by a CA-based One-time Password (OTP) authentication which is a randomized evolution. The experiments prove the security of the proposed scheme.

The safety of electrode-tissue interface under electrical neural stimulation is a critical matter and thus precise control of the electrode voltage needs to be warranted. Analytical study on the electrode potential profile during electrical stimulation justifies the need of using a closed-loop system to regulate the electrode voltage. A neural stimulator with cancellation of excessive charge is proposed. The design procedure and methodology are presented to provide general guidelines for similar system designs. Simulation results demonstrate that neural stimulation safety can be achieved by the proposed design methodology.

New memristors-based neuronal spike event generator is introduced. By using the dynamic properties of conditional resistance switching of a practical bistable memristive device, the neuronal action potential is generated describing both the integrate-and-fire spiking events and the long enough refractory period of nerve membrane cells. The memristor offers the dual time-constants which model the unbalanced charging and discharging periods of the spike signals. With a Pt/TiO 2 /Pt memristive device having the R OFF /R ON resistance ratio of 3000, the memristor-based spike generator offers spike trains with about 0.03% duty.

Until recently, two-dimensional (2-D) cellular automata (CA) pseudorandom number generator (PRNG) research areas have been done based on von Neumann with linear neighborhood relationship. Although the linear neighborhood relationship has an excellent random quality, its cycle length is less than the linear neighborhood relationship. The cycle length is an important w.r.t. cryptographically secure PRNG because of the property of non-prediction for next sequence.

This chapter reviews recent technology trends in memristive analog and digital electronics, with particular attention to programmable analog and digital circuits, ultra-dense nonvolatile resistive memory architectures, and zero leakage nonvolatile logic gates. A reconfigurable nonvolatile computing platform that harnesses memristor properties is used to deploy massive local nonvolatile memories and advance computing capabilities with much lowered energy consumption than the conventional charge-based VLSI systems. With application of memristive devices for nonvolatile memories, programmable interconnects, stateful logic gates, and nonvolatile latches with high integration density and CMOS compatibility, combining memristor technology with the prevailing CMOS technology poses to prolong the Moore’s Law beyond the hitherto observed technological limitations.

This paper introduces a complementary architecture of memristive devices based passive memories whose unit memory cell is composed of vertically stacked or horizontally placed two memristive devices. This complementary memory architecture does not require sense resistors for cell readout, and thus significantly reduces the memory design complexity by not requiring the design optimization process for the sense resistance. The complementarily written memory array exhibits data-pattern independent voltage detection performance as well as regulated much smaller current consumption compared to the conventional non-complementary passive resistive memories.

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine-grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.

Accurate estimation of temperature profiles from the underlying power dissipation profiles has become an important tool for chip designers and reliability engineers due to increasing power dissipation in ICs and associated thermal effects. IC's surface temperature is conventionally calculated by finite element or finite difference solvers. These methods yield accurate results but the computation time could be several hours to obtain accurate dynamic temperature profiles with high spatial resolution. Previously, we have developed an ultra fast IC temperature profile calculation technique, named as Power Blurring (PB), which dramatically reduces the computation time by a factor of more than a thousand and keeps the error within 5% comparing to finite element analysis done by ANSYS. In this paper, the power blurring method is validated against experimental measurements using a thermal test chip which was designed based on 5-stage ring oscillators. The simulation results and the measurement data show good agreements.

Reversible data hiding is very useful for some extremely image such like medical images and military images. In the reversible data hiding schemes, some schemes are good performance at hiding capacity but have a bad stego image quality, some schemes are good stego image quality but have a low hiding capacity. It is difficult to find the balance between the hiding capacity and stego image quality. In this paper, a novel reversible data hiding scheme is proposed. The proposed scheme uses a new embedding method, which is called Even-Odd embedding method, to keep the stego image quality in an acceptable level, and uses the multi-layer embedding to increase the hiding capacity. The experimental results demonstrate that no matter how much secret data is embedded, the stego image quality is about 54dB in the proposed scheme.

This paper demonstrates that memristors can be used to form a fine resolution programmable resistance without perturbations by parasitic components. By exploiting the memristor characteristics, fine resolution programmable memristance is achieved by varying the amount of charges flowing or flux across the memristor. Under the same circuit configuration with same or even less amount of parasitics, memristance is reconfigured with fine resolution by controlling the input pulse width and its frequency. This paper shows an example of pulse programmed memristors and their analog circuit applications.

Sensor networks are expected to be used at anywhere in the near future and recently their security problems have been rising. Due to the limited computing power of senor nodes, it is impossible to use asymmetric cryptography approaches for the session key establishment or to apply advanced encryption method such as AES and DES for the data encryption. In this paper, therefore, we propose a key establishment and a data encryption scheme for secure and energy-efficient data transmission in wireless sensor networks (WSNs). The proposed schemes just treat simple operations as a message authentication code (MAC), exclusive-OR (XOR) and time-spacing key derivation function (TSDF). Additionally, the security of the proposed protocols is analyzed.

This paper describes a radio architecture and circuit implementation results for Korea/Japan standards of 5.8 GHz DSRC systems. By characterizing specific system features concerning practical environments such as communication cell area and in-vehicle temperature, we extract detailed design specifications and show a practical system implementation. Also, we introduce a new receiver sensitivity control method which has superior signal quality over the conventional ones by gating the detected RX data with respect to the received RSSI, without degradation of receiver SNR. When the complete transceiver circuit is integrated on a chip using 0.18 mum CMOS technology, the transmitter carries up to +10.5 dBm of output power and the receiver has less than 17 dB of system noise figure. The active current consumptions are 102 mA and 52 mA during TX- and RX- modes, respectively, for 1.8V supply voltage.

As IEEE 802.11 networks in a BSS are increasingly used to carry VoIP, concerns about QoS arise. The overall delay of all VoIP flows drastically increases when the number of VoIP sources approaches the capacity, due to the characteristics of CSMA/CA. We propose a novel call admission control with the Queue size Prediction using Computation of Additional Transmission (QP-CAT) to avoid admitting an excessive number of simultaneous calls. In QP-CAT, an AP can accurately predict the effect of new VoIP flows on the delay of existing VoIP flows by predicting its queue size, before the new VoIP flow is actually admitted. It can be easily extended to support 802.11e so that the AP can predict the effect even when background traffic exists with VoIP traffic under 802.11e.

Okubo et al. proposed a hash-chain based authentication protocol which protects users' location privacy and anonymity with strong forward security. However, Li et al. claimed that the hash-chain calculation must be a burden on low-cost RFID tags and gives back-end servers heavy calculation loads since the numbers for hash computation are required in a hash chaining technique. Thus, the non-group cellular automata chaining technique is adopted composed only of logical bitwise operations, in order to maintain both security guarantees and a low-cost construction.

We measured the capacity for VoIP traffic in an 802.11b test-bed and compared it with the theoretical capacity and our simulation results. We identified factors that have been commonly overlooked in past studies but affect experiments and simulations. We found that in many papers the capacity for VoIP traffic has been measured via simulations or experiments without considering those factors, showing different capacity in each paper. After these corrections, simulations and experiments yielded a capacity estimate of 15 calls for 64 kb/s CBR VoIP traffic with 20 ms packetization interval and 34 calls to 36 calls for VBR VoIP traffic with 0.39 activity ratio.